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Since our founding in 1995 by Stefen Boyd, we have provided outstanding solutions for:
  • Verilog Expert Witness - Verilog analysis for patent infringement
  • ASIC Verification - Verilog, Vera, Specman
  • ASIC Design
  • Introduction and Advanced Verilog Training

With our expertise in Verilog-HDL, we can make your design and verification resources more efficient. One of our strengths is rapid understanding of your design and it's verification requirements. This translates to near instantaneous productivity.

We take the initiative to identify problems and present solutions that cut your time to market.

Mr. Boyd

Our founder is a Verilog expert who participates in the IEEE standardization of Verilog, and has extensively used Verilog for design and verification. He has been actively involved in the Verilog 1364-2001 standardization as a member of the Behavioral Task Force since 1997. This Task Force was responsible for the synthesis and verification enhancements to the language. He is also a member of the IEEE 1364.1 Verilog RTL Synthesis Interoperability Working Group, and of the Accellera HDL++ Working Group, which is adding further enhancements to the Verilog language for synthesis and verification. He has also supported patent litigation as a Verilog Expert Witness.

Mr. Boyd has authored conference papers on verification for the Synopsys Users Group ("SNUG") and HDLCon. He is also a certified instructor for the Introduction and Advanced Verilog for Synthesis and Verification courses developed by Sunburst Design.

Copyright ©2002 Boyd Technology, Inc.
Last revised: Mon Jun 16, 2003