From: Anders Nordstrom (andersn@nortel.ca)
Date: Thu Oct 09 1997 - 12:19:12 PDT
BAD MSG:
Dear Behavioural Task Force Members,
ontent-Length: 9378
X-Lines: 304
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Status: RO
Please review the proposals for the 1364 errata items included below and
be prepared to vote on them on the BTF conference call on October 29.
This email was sent both to the new BTF mailing list and the 1364core reflector.
Starting October 13, I will only send working email such as this one to
the BTF reflector. To add yourself to the mailing list, send an email to
btf-request@boyd.com and include "subscribe" in the message body.
Regards,
Anders Nordstrom
<p>+-----------------------------------------------------------------------+
| Anders Nordstrom |
| Senior ASIC Designer |
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| Northern Telecom Ltd. Email: andersn@nortel.ca |
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Subject: BTF - BE02 - Annex A - $nocheck clarification
Behavioral Task Force - Errata Submission
Assigned Errata Number: BE02
Enhancement Name (Description): Annex A - $nocheck clarification
Date Submitted: 970505
Requestor: graham@compass-da.com
(Paul Graham)
Status: Proposal
Analyzed by: Anders Nordstrom
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
Annex A. Under the syntax for system_timing_check, there is no listing
for $nocheck, even though $nocheck is listed in chapter 14 as a system
timing check.
Proposal:
$nocheck in the errata is a typo, it should be $nochange.
Add $nochange (reference_event,data_event,start_edge_offset,
end_edge_offset[,notifier]);
to system_timing_checks in the BNF in section A.7
**************************************************************************
Subject: BTF - BE20 - inter_assignment_timing_control_statement
Behavioral Task Force - Errata Submission
Assigned Errata Number: BE20
Errata Name (Description): who cares about inter_assignment_
timing_control_statement
Section: 9.7.6
Date Submitted: 960919
Requestor: Daniel Barclay
Status: Proposal
Analyzed by: Anders Nordstrom
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
intra_assignment_timing_control_statement is defined in Syntax 9-12
but not referred to anywhere in the grammar.
Proposal:
Add the syntax in box 9-12 on page 117 to section A.6
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Subject: BTF - BE34 - can '?' appear as a digit?
Behavioral Task Force - Errata Submission
Assigned Errata Number: BE34
Errata Name (Description): can '?' appear as a digit?
Section: 2.5.1
Date Submitted: 970701
Requestor: Paul Graham
Status: Proposal
Analyzed by: Mike McNamara
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
The syntax box excludes '?' from appearing as a binary_digit,
octal_digit, or hex_digit. The syntax in Annex A also does not allow '?'.
Yet the text in section 2.5.1 says that '?' may appear. Which is correct?
Proposal:
Allow "?" to appear in binary, octal and hexadecimal digits. The "?"
character is equivalent to the "z" or "Z" character.
Update the syntax in box 2-1 on page 6 and in section A.8
**************************************************************************
Subject: BTF - BE38 - Section 2.5.1 Incorrect Reference
Behavioral Task Force - Errata Submission
Assigned Errata Number: BE38
Errata Name (Description): Section 2.5.1 Incorrect Reference
Section: 2.5.1
Date Submitted: 961230
Requestor: Anders Nordstrom
Status: Proposal
Analyzed by: Mike McNamara
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
* page 7: second paragraph from the bottom above the example:
There is a reference to section 8.1.4 when refering to
a question mark in a user-defined-primitive state table.
Section 8.1.4 do not mention the use of question marks.
Proposal:
Change the reference to table 8.1
**************************************************************************
Subject: BTF - BE44 - Empty Ports
Behavioral Task Force - Errata Submission
Assigned Errata Number: BE44
Errata Name (Description): Empty Ports
Section: 12.1.2
Date Submitted: 970531
Requestor: Mitchell Perilstein
Status: Proposal
Analyzed by: Mike McNamara
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
Section 12.1.2 says,
A connection can be a simple reference to a register or a net
identifier, an expression, or a blank. An expression can be used for
supplying a value to a module input port. A blank module connection
shall represent the situation where the port is not to be connected.
Judging by XL behavior, the following sentence should be added.
If all module connections are not connected, the commas are
optional. For example, the following are identical.
flop f1(,,,);
flop f1();
This sentence could also go near the other relevant paragraph:
The list of module connections shall be provided only for modules
defined with ports. The parentheses, however, are always
required. When a list of module connections is given, the first
element in the list shall connect to the first port, the second to
the second port, and so on. See section12.3 for a more detailed
discussion of ports and port connection rules.
<p>Proposal:
Add the following text after the fourth paragraph under the
syntax box on page 137.:
If all module connections are not connected, the commas are
optional. For example, the following are identical.
flop f1(,,,);
flop f1();
Add the following text just before "Examples:" on page 137:
The list of module connections shall be provided only for modules
defined with ports. The parentheses, however, are always
required. When a list of module connections is given, the first
element in the list shall connect to the first port, the second to
the second port, and so on. See section12.3 for a more detailed
discussion of ports and port connection rules.
**************************************************************************
Subject: BTF - BE48 - Identifier length
Behavioral Task Force - Errata Submission
Assigned Errata Number: BE48
Errata Name (Description): Identifier length
Section: 2.7, page 11
Date Submitted: 12/8/96
Requestor: Stu Sutherland
Status: Proposal
Analyzed by: Mike McNamara
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
The note states the maximum identifier length is "at least
1024
characters". Submitter recalls the 1364 committee had decided on 64
characters. Need to check official minutes.
Proposal:
Reject the errata and keept the note on page 11 as is.
**************************************************************************
Subject: BTF - BE51 - Register keyword error
Behavioral Task Force - Errata Submission
Assigned Errata Number: BE51
Errata Name (Description): Register keyword error
Section: 3.2.2, page 14
Date Submitted: 12/8/96
Requestor: Stu Sutherland
Status: Proposal
Analyzed by: Mike McNamara
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
The second sentance, "The keyword for the register data type
is reg.", is not correct, as there are several keywords for the register data
type, as listed the syntax box that follows. Suggest the sentance be struck
from the LRM.
Proposal:
Remove the sentence: "The keyword for the register data type
is reg." on page 14.
**************************************************************************
Subject: BTF - BE60 - Assignment equals update
Behavioral Task Force - Errata Submission
Assigned Errata Number: BE60
Errata Name (Description): Assignment equals update
Section: 6, page 50
Date Submitted: 12/8/96
Requestor: Stu Sutherland
Status: Proposal
Analyzed by: Anders Nordstrom
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
The third paragraph states that the left-hand side and rigt-
hand side of an assignment is separated by the "equals ( = ) character". It
should state the "equals ( = ) character or less-than-equals ( <= ) character
pair".
Proposal:
Add: "or, in the case of non-blocking procedural assignment, the
less-than-equals ( <= ) character pair" to the sentence in the
third paragraph.
Also change the sentence "There are two additional forms...." to
"There are two additional forms of assignments, assign / deassign and
force / release which are called Procedural Continous Assignments,...."
**************************************************************************
Subject: BTF - BE63 - Repeat count zero
Behavioral Task Force - Errata Submission
Assigned Errata Number: BE63
Errata Name (Description): Repeat count zero
Section: 9.7.6, page 118
Date Submitted: 970909
Requestor: Tom Fitzpatrick
Status: Proposal
Analyzed by: Anders Nordstrom
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
Section 9.7.6, page 118, addition to first paragraph.
I would like to say "If the repeat count is <= 0 at the time
of evaluation, the assignment occurs immediately."
Proposal:
Add the sentence below to the first paragraph in section 9.7.6:
"If the repeat count is <= 0 at the time of evaluation, the assignment
occurs immediately."
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