From: mac@silicon-sorcery.com
Date: Mon Oct 27 1997 - 13:43:22 PST
Steve Meyers writes:
>
> Subject: BTF - BE65 - Real conversion in expressions
>
> Behavioral Task Force - Errata Submission
>
> Assigned Errata Number: BE65
> Errata Name (Description): Real conversion in expressions
> Section: 3.9.2 page 25
> Date Submitted: 970923
> Requestor: Steve Meyer
>
> Status: Submitted (priority not yet assigned)
>
> Errors found in the Verilog LRM (IEEE 1364-1995).
>
> Details:
>
> I do not think the LRM's explanation of conversion of reals in
> expressions is right. Section 3.9.2, paragraph 2 explicitly states
> conversion to real takes place on assignment implying that
I do not agree that there is a implication as you state it.
> non reals in expressions (where operator is defined for real
> operands) are not converted to real but rather a syntax error has
> occurred, but then one of the examples at bottom of section 3.10
> shows a parameter expression with a real and non real constant. I
> assume section 3.9.2 should say that implicit conversion to real
> occurs for mixed type expressions. Or is the text correct and the
> example wrong? Also I think the LRM should document if there is a
> difference between constant expressions and variable expressions
> i.e. if "3.0 + 4" is legal but "r + i" where r is declared real and
> i declared integer is not legal syntax following text in section
> 3.9.2.
> Steve Meyer
My proposal is to change the sentance from
Implicit conversions shall take place when a net or register is
assigned to a real.
to:
Implicit conversions shall take place when an expression is
assigned to a real.
<p>-mac
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