From: Mike McNamara (mac@silicon-sorcery.com)
Date: Tue Dec 02 1997 - 11:40:17 PST
adamk@cyrix.com writes:
> module test;
>
> reg [21:0] b;
> initial begin
> // This is a delay of 32.
> b = # 32 'h 20 - 10;
> //b = #32'h20 - 10; So is this.
> end
> initial $monitor($time, ,,b);
> endmodule
Again, delay is "special"; by my understanding XL takes the first
'thing with no embedded white space' after the # as the delay; to get
the above to behave diferently you need to do as in +define+T3:
module test;
integer b;
initial begin
`ifdef T1
b = # 32 'h 40 - 10; $display("expect delay of 32, value %d",'h40 - 10);
`endif
`ifdef T2
b = #32'h40 - 10; $display("expect delay of 64, value %d",-10);
`endif // ifdef T2
`ifdef T3
b = #(32 'h 40) - 10; $display("expect delay of 64, value %d",-10);
`endif
end
initial $monitor($time," %d",b);
endmodule
Could you try the above on simulators you have access to?
Please run
vxl +define+T1 test.v
vxl +define+T2 test.v
vxl +define+T3 test.v
for each implementation of a vxl you have, and report the results
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