From: Mike McNamara (mac@silicon-sorcery.com)
Date: Tue Dec 02 1997 - 13:25:56 PST
Chris Spear writes:
>
> Here are the results from VCS 4.0.2
>
> Command: vcs -R sample.v +define+T1
> Chronologic Simulation VCS Release 4.0.2 Tue Dec 2 15:35:37 1997
> 0 x
> expect delay of 32, value 54
> 32 54
>
>
> Command: vcs -R sample.v +define+T2
> Chronologic Simulation VCS Release 4.0.2 Tue Dec 2 15:36:01 1997
> 0 x
> expect delay of 64, value -10
> 32 54
>
>
> Command: vcs -R sample.v +define+T3
> Chronologic Simulation VCS Release 4.0.2 Tue Dec 2 15:36:20 1997
> 0 x
> expect delay of 64, value -10
> 64 -10
>
>
I guess my memory is not right; I thought I'd implemented T2 as the
test expected. I'd like to see what Verilog-XL says (anyone care to
run the test?)
Frontline appears to agree with VCS.
-mac
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:52:32 PDT
and
sponsored by Boyd Technology, Inc.