From: Thomas Fitzpatrick (tfitz@cadence.com)
Date: Tue Dec 09 1997 - 06:40:49 PST
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Proposal for changes to IEEE 1364 Spec to support Signed Arithmetic
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Syntax 2-1 (P. 6)
decimal_base ::= '[s|S]d | '[s|S]D
binary_base ::= '[s|S]b | '[s|S]B
octal_base ::= '[s|S]o | '[s|S]O
hex_base ::= '[s|S]h | '[s|S]H
Page 7 (2nd Paragraph)
The second token, a base_format, shall consist of a letter
specifying the hase for the number, optionally preceded by the single
character 's' to indicate a signed quantity, preceded by the single quote
character ('). Legal base specifications are ... respectively.
Page 7 (6th Paragraph)
Simple decimal numbers without the size and the base format shall
be treated as signed integers, whereas the numbers specified with the base
format shall be treated as signed integers if the 's' designator is
included, or as unsigned integers if the base format only is used. The 's'
designator does not affect the bit pattern specified, only its interpretation.
Page 8 (Top - Using sign with constant numbers)
4'shf // this denotes the 4-bit number '1111', to be interpreted
// as a 2's complement number, or '-1'. This is equivalent
// to -4'h1
-4'sd15 // This is equivalent to -(-4'd1), or '0001'.
Syntax 3-1 (p. 14)
net_declaration ::=
net_type [vectored|scalared] [signed|unsigned] [range] [delay3]
list_of_net_identifiers;
| trireg [vectored}scalared] [signed|undigned] [charge_strength] [range]
[delay3] list_of_net_identifiers;
| net_type [vectored|slalared] [drive_strength] [range] [delay3]
list_of_net_decl_assignments;
Syntax 3-2 (p. 14)
reg_declaration ::= reg [signed|unsigned] [range]
list_of_register_identifiers;
Page 15 (Section 3.3.1 Specifying vectors - 3rd Paragraph)
Vector nets and registers shall obey laws of arithmetic modulo 2
to the power n(2^n), where n is the number of bits in the vector. Vector
nets and registers shall be treated as unsigned quantities, unless the net
or register is declared to be signed.
Examples:
reg signed [3:0] signed_reg; // 4-bit vector in range -8 to 7
Table 4-1 (p. 28)
Replace the "Left Shift" and "Right Shift" rows with the following:
<< Logical Left Shift
>> Logical Right Shift
<<< Arithmetic Left Shift
>>> Arithmetic Right Shift
Table 4-3 (p. 29)
Add the arithmetic shift operators to the last row:
<<,>>,<<<,>>> Shift
Table 4-4 (p. 29)
Add the arithmetic shift operators to the 4th row:
<< >> <<< >>>
Section 4.1.3 (p. 30)
Integer numbers can be used as operands in expressions. An integer
number can be expressed as:
- An unsized, unbased integer (e.g., 12)
- An unsized, based integer (e.g., 'd12, 'sd12)
- A sized, based integer (e.g., 16'd12, 16'sd12)
A negative value for an integer with no base specifier shall be
interpreted differently than for an integer with a base specifier. An
integer with no base specifier, or with a signed base specifier, shall be
interpreted as a signed value in 2's complement form. An integer with an
unsigned base specifier shall be interpreted as an unsigned value.
Example:
This example shows three ways to write the expression "minus 12
divided by 3." Note that -12 and -'d12 both evaluate to the same 2's
complement bit pattern, but, in an expression, the -'d12 loses its
identity as a signed negative number.
integer IntA;
IntA = -12 / 3; // The result is -4.
IntA = -'d 12 / 3; // The result is 1431655761.
IntA = -'sd 12 / 3; // The result is -4
IntA = -'4sd 12 / 3; // -4'sd12 is the negative of the 4-bit quantity
// 1100, which is -4. -(-4) = 4.
Table 4-8 (p. 32)
Data Type Interpretation
--------- --------------
unsigned net Unsigned
signed net Signed, 2's complement
unsigned reg Unsigned
signed reg Signed, 2's complement
integer Signed, 2's complement
time Unsigned
real,realtime Signed, floating point
Example (p. 32) [add the following examples]
reg signed [15:0] regS;
regS = -12 / 3; // expression result is -4. regS is a signed register
regS = -4'sd12 / 3; // expression result is 1. -4'sd12 is actually 4
// The rules for integer division yield 4/3 = 1
Section 4.1.12 (p. 36)
There are two types of shift operators: the logical shift
operators, << and >>, and the arithmetic shift operators, <<< and >>>.
The left shift operators, << and <<<, will shift their left operand to
the left by the number of bit positions given by the right operand. In
both cases, the vacated bit positions shall be filled with zeroes. The
right shift operators, >> and >>>, will shift their left operand to the
right by the number of bit positions given by the right operand. The
logical right shift shall fill the vacated bit postions with zeroes, but
the arithmetic right shift shall fill the vacated bit positions with the
value of the most-significant (i.e. sign) bit of the left operand.
If the rith operand has an unknown or high-impedance value, then the
result shall be unkown. The right operand is always treated as an
unsigned number.
[ add a second example ]
Example:
module ashift;
reg [3:0] start, result;
initial begin
start = 4'b1000;
result = start >>> 2;
end
endmodule
In this example, the register result is assigned the binary value
1110, which is 1000 shifted to the right two positions and sign-filled.
NEW SECTION
4.5 Signed Expressions
Controlling the sign of an expression is important if consistent results
are to be achieved. In addition to the rules outlined in this following
sections, two system functions may be used to handle typ ecasting on
expressions: $signed() and $unsigned(). These functions will evaluate the
input expression and return a value with the same size and value of the
input expression and the type defined by the function:
$signed - returned value is signed
$unsigned - returned value is unsigned
Example
reg [7:0] regA;
reg signed [7:0] regS;
regA = $unsigned(-4); // regA = 4'b1100
regS = $signed(4'b1100); // regS = -4
4.5.1 Rules for expression types
The following are the rules for determining the resulting type of an
expression:
1. Expression type depends only on the operands. It does not depend on the
LHS (if any).
2. Decimal numbers are signed.
3. Based_numbers are unsigned, except where the 's' notation is used in the
base specifier (as in "4'sd12").
4. Parameters are signed if and only if the RHS expression assigned to the
parameter is signed .
5. Bit-select results are unsigned, regardless of the operands.
6. Part-select results are unsigned, regardless of the operands.
7. Concatenate results are unsigned, regardless of the operands.
8. Comparison results (1, 0) are unsigned, regardless of the operands.
9. Reals converted to integers by type coercion are signed
10. The sign and size of any self-determined operand is determined by the
operand itself and independent of the remainder of the expression.
11. For non-self-determined operands the following rules apply:
if any operand is real, the result is real.
elseif any operand is unsigned, the result is unsigned, regardless
of the operator
elseif all operands are signed, the result will be signed,
regardless of operator, except as noted.
4.5.2 Steps for evaluating an expression
1. Determine the expression size based upon the standard rules of expression
size determination.
2. Determine the sign of the expression using the rules outlined in
Section 4.5.1
3. Coerce the type of each operand of the expression (excepting those which
are self-determined) to the type of the expression.
4. Extend the size of each operand (excepting those which are self-determined)
to the size of the expression. Perform sign extension if and only if the
operand type (after type coercion) is signed.
4.5.3 Steps for evaluating an assignment
1. Determine the size of the RHS by the standard assignment size determination
rules (see section 4.4)
2. If needed, extend the size of the RHS, performing sign extension if
and only if the type of the RHS is signed.
4.5.4 Handling 'X' and 'Z' in signed expressions
If a signed operand is to be resized to a larger signed width and the
value of the sign bit is "X", the resulting value will be bit filled with
"X"s. If the sign bit of the value is "Z", then the resulting value will
be bit filled with "Z"'s. If any bit of a signed value is "X" or "Z"
then any non logical operation involving the value will result in the
entire resultant value being an "X" and the type consistent with the
expressions type.
Section 10.3.1 (p. 129 - 2nd paragraph)
A function declaration shall begin with the keyword function, followed by
the optional signed designator and then the range or type of the return
value from the function, followed by the name of the function and a
semicolon...
Syntax 10-3 (p. 129)
function_declaration ::=
function [signed] [range_or_type] function_identifier;
function_item_declaration {function_item_declaration}
statement
endfunction
Syntax 12-4 (p. 142)
input_declaration ::= input [signed] [range] list_of_port_identifiers;
output_declaration ::= output [signed] [range] list_of_port_identifiers;
inout_declaration ::= inout [signed] [range] list_of_port_identifiers;
Section 12.3.2 (p. 142 - 2nd paragraph)
A port can be declared in both a port declaration and a net or register
declaration. If a port is declared as a vector, the range specification
between the two declarations of a port shall be identical. If a port is
declared as signed, then the corresponding net or register shall also be
declared as signed.
NEW SECTION 12.3.9 Connecting signed values via ports
The signed attribute will not cross hierarchy. In order to have
the signed type cross hierarchy, the signed keyword must be used in the
object's declaration at the different levels of hierarchy. Any
expressions on a port will be treated as any other expression in an
assignment. It will be typed, sized, evaluated and the resulting value
assigned to the object on the other side of the port using the same rules
as an assignment.
P. 624-628 vpi_user.h
New generic object properties
#define vpiSigned /* TRUE for following object that have the signed
attribute: vpiIODecl and any object in the
expression class */
New expression properties /* subtypes of vpiOpType */
#define vpiArithLShiftOp 41 /* Arithmetic left shift */
#define vpiArithRShiftOp 42 /* Arithmetic right shift */
New system taskfunc properties /* subtype of vpiSysFuncType */
#define vpiSysFuncSignesSized 5 /* returns signed sized */
-- --------------- Tom FitzpatrickCadence Design Systems Technical Marketing Manager Product Engineering Logic Design & Verification Business Unit (978)446-6438 x6438
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