From: Shalom Bresticker (shalom@msil.sps.mot.com)
Date: Wed Dec 10 1997 - 23:50:09 PST
> From owner-btf@boyd.com Tue Dec 9 20:33:04 1997
> To: "Thomas Fitzpatrick" <tfitz@cadence.com>, btf@boyd.com
> From: Stuart Sutherland <stuart@sutherland.com>
> Subject: Re: B19 - Signed Arithmetic Proposal
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> 3. The proposal does not cover implicit net declarations. I suggest adding
> a note that implicit nets shall always be unsigned. This should go into
> the sections that discuss signed data types and section 3.5 on implicit
> data types. (Note that section 3.5 has other problems as well, since it
> mandates that implicit declarations will always be scalar, which is not true).
Why is that not true ?
So far as I know, in Verilog-XL, for example, it IS true.
That is, you cannot implicitly declare a vector net.
The compiler either assumes it to be a scalar, or
issues an error message that the net is not declared.
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Shalom Bresticker email: shalom@msil.sps.mot.com
Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522444
http://www.motorola-semi.co.il/
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