Re: BTF - B19- Cadence signed arithmetic proposal

From: Thomas Fitzpatrick (tfitz@cadence.com)
Date: Wed May 07 1997 - 07:14:21 PDT

There were a few issues that came up at Monday's discussion of this proposal,
and I'd like to address some of them now.

  The number of bits in a signed division operation: (example -8/-1 = 8)
        If the size of the operation is not big enough to hold the full value
of the result, then the result is truncated to the length of the operation. The
errant behavior of the prototype I mentioned is a bug and has been pcr'd.

  What to do with "-4'd1": Mac mentioned that Verilog-XL has always treated
this as if the unary "-" operation is applied to the constant "4'd1". That's
not quite true. According to the 1364 spec (p 30), "an integer with a base
specifier shall be interpreted as an unsigned value." Therefore, where the
proposal lists
        -4'd1 // 4 bit unsigned decimal -1
if this were assigned to an integer, or a signed reg of more than 4 bits, the
value should be zero-extended. Because based numbers are interpreted as
unsigned, we proposed the
        -4'sd1 // 4 bit signed decimal -1
notation to be able to specify a signed, based number.

        All of the other issues were simply places where the spec was not as
rigourous as it should be, but the intended behavior is as we all expected. I
will be updating the proposal shortly.

Thanks,
-Fitz 

-- 
Tom Fitzpatrick

Cadence Design Systems                 Technical Marketing Manager
Product Engineering                    Logic Design & Verification Group
(508)446-6438                          x6438

This archive was generated by hypermail 2.1.4 : Mon Jul 08 2002 - 12:54:40 PDT and
sponsored by Boyd Technology, Inc.