From: Clifford E. Cummings (cliffc@europa.com)
Date: Fri May 02 1997 - 08:56:21 PDT
This feature would not be synthsizable (it is not synthesizable in VHDL,
either) but the feature is nice for testbenches.
VHDL permits initial assignment to registers and I consider it to be a nice
feature. I would support the version that Mac has shown below.
<p>Subject: BTF - B14 - Initial assignments in register
Behavioral Task Force - Enhancement Request
Assigned Enhancement Request Number: B14
Enhancement Name (Description): Initial assignments in register declarations
Date Submitted: 970319
Requestor: adamk@cyrix.com (Adam Krolnik)
Status: RO
Is enhancement intended to be synthesizable?: No
6. Initializers on registers.
It is tedious and verbose to have to write:
reg[3:0] a;
initial a = 4'h4;
Rather a better combination would be:
reg[3:0] a = 4;
From: mac@silicon-sorcery.com
Date: Wed, 19 Mar 97 14:22:50 PST
not unreasonable.
I would offer medium support for this proposal, with the note that
since initial blocks already aren't synthesizeable, this simply adds
more cruft for synopsis to ignore. You might want to consider:
reg [31:0] a = 0, b = 1, c = 2;
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