From: Clifford E. Cummings (cliffc@europa.com)
Date: Fri May 02 1997 - 08:52:55 PDT
Subject: BTF - B13 - Mutable bit selects
Behavioral Task Force - Enhancement Request
Assigned Enhancement Request Number: B13
Enhancement Name (Description): Mutable bit selects
Date Submitted: 970319
Requestor: adamk@cyrix.com (Adam Krolnik)
Status: RO
Is enhancement intended to be synthesizable?:
5. Mutable bit selects
It is tedious (and confusing without the comment) to write this code.
reg [15:0] a, b;
integer i;
a = a | (1 << i); //in place of a[i] = 1;
a = (a & ~(4'hf << i)) | (((b >> 2) & 4'hf) << i); // a[i+3:i] = b[5:2];
A HDL language should allow programmatic specification of bit selects,
rather than resorting to shifting and or'ing and and'ing. This construct is
simply removing a hinderance in specification (for software writing and
understanding.) It's not for ease of description of hardware. Also for
examining bits of a register, one has to resort to shifting to get to them. E.g.
for (i = 0; i < 32; i = i + 1)
begin
// instead of next 2 statements, how about:
// if (a[i]) ...
if (a[0]) begin end
a = a >> 1;
end
<p>From: mac@silicon-sorcery.com
Date: Wed, 19 Mar 97 14:22:50 PST
Hmm.I think there is some misunderstanding here. Verilog
currently supports variable bit selects of both wires and
registers. So, in your example, each of the comments would work just
fine. Verilog doesn't support variable part selects, and there is
currently a proposal for the addition of these.
i.e.:
always @(clk)
for (i = 0; i < 32; i = i + 1)
if (a[i]) $display($stime,,"bit %d of b is true",i);
should work in any simulator.
<p>From: Adam Krolnik <adamk@cyrix.com>
Date: Fri, 21 Mar 97 09:20:37 +0600
Thanks! I never considered the degenerate case (single bits) would work.
One other question: Has there been any discussion of defining what happens
to outputs of tasks when a task is disabled? Also what happens to registers
assigned a value with a non-blocking assignment when their block is disabled?
From: mac@silicon-sorcery.com
Date: Fri, 21 Mar 97 09:59:26 PST
The discussion resulted in the current standard. XL and VCS behave
differently in these two cases. The committee is composed of different
members now, perhaps a new proposal would be resolved differently.
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