From: Clifford E. Cummings (cliffc@europa.com)
Date: Fri May 02 1997 - 08:28:14 PDT
I do not favor this enhancement. This functionality is just as easy to
implement with an always block, plus the last time I benchmarked continuous
assignments against equivalent always blocks using Verilog-XL, the always
block implementation was actually faster (may not me true for all Verilog
simulators).
Also, if we do pass "BTF - B08 - Combinational sensitivity list @*", The
always block implementation will be even easier.
Regards - Cliff Cummings
Subject: BTF - B12 - Continuous assignment case expressions
Behavioral Task Force - Enhancement Request
Assigned Enhancement Request Number: B12
Enhancement Name (Description): Continuous assignment case expressions
Date Submitted: 970319
Requestor: adamk@cyrix.com (Adam Krolnik)
Status: RO
Is enhancement intended to be synthesizable?:
4. Case expressions.
Assignment statements should have an expression case statement available.
E.g.
assign data_out = case(mux_select)
2'h0: mux_1;
2'h1: mux_2;
2'h2: mux_3;
2'h3: mux_4;
endcase
This case statement returns a value equal to the size of the expression
selected.
From: mac@silicon-sorcery.com
Date: Wed, 19 Mar 97 14:22:50 PST
This isn't much different than the Conditional operator
(4.1.13), and isn't as powerful:
assign data_out = (mux_select == 0) ? mux1 :
(mux_select == 1) ? mux2 :
(mux_select == 2) ? mux3 :
(mux_select == 3) ? mux4 : 'bx;
Also all tools currently support the conditional operator.
My support for this proposal would be very weak, as it really
doesn't add much to the langauge, except another way to do something
one can already express. Further, these declarative case statements
would appear tantalizingly similar to the behavorial case statement,
however we would have to include all the declarative restrictions: for
example, it would be illegal to call a task from this declarative
case, or make any assignments to other variables, and so on.
Currently I hate the fact that there are two different
syntaxes for the word "assign": one is the declarative assign, that
can only act on wires,and must appear at module scope; and the other
is the procedural assign, which can only act on registers, and must be
in behavioral scope, and really is just a version of force.
From: Adam Krolnik <adamk@cyrix.com>
Date: Fri, 21 Mar 97 09:20:37 +0600
You are correct, however I have seen several designers create a function
just to access the case operator. Speaking of the 'force' construct, is it
necessary to restrict part-selects (or bit-selects) as the operand. I think
one simulator may have allowed this, but not others.
From: mac@silicon-sorcery.com
Date: Fri, 21 Mar 97 09:59:26 PST
Forces are allowed to bit and part selects of wires, but not to registers.
XL adds the additional restriction that one can only perform bit and part
selects of any form to wires that are declared "scalar" (or at least are not
declared "vectored").
//********************************************************************//
// Cliff Cummings E-mail: cliffc@europa.com //
// Sunburst Design Phone: 503-579-6362 / FAX: 503-579-7631 //
// 15870 SW Breccia Dr., Beaverton, OR 97007 //
// //
// Verilog & Synthesis Training / On-Site Training //
// Verilog, VHDL, Synopsys, LMG, FPGA, Consulting and Contracting //
//********************************************************************//
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:54:40 PDT
and
sponsored by Boyd Technology, Inc.