From: Clifford E. Cummings (cliffc@europa.com)
Date: Fri May 02 1997 - 08:00:47 PDT
Could I suggest a couple of modifications to this request?
module acontroller;
parameter AMSB = 31, DMSB = 7;
input req, reset, clock, start;
input[7:0] data;
output reg ack, end, full, empty;
output error;
output reg [AMSB:0] ad;
output reg [DMSB:0] head;
output reg [3:0] cbe;
First: Instead of making a (port list), I would propose an I/O list similar
to VHDL. Believe me I am not trying to make Verilog into VHDL but they
actually had a good idea here (don't let any VHDL-types know I said that ;-)
Reason: This allows parameter declarations before the I/O list to create
parameterized modules.
Second: I would recommend the syntax to be <I/O type> <optional net_reg
type> <optional_range> <IO_list>. I believe it is easier to scan the I/O
list this way.
Third: If both a port list and I/O list are declared, the port list
determines the port order, otherwise the I/O list determines the port order.
This is only important when instantiating modules with positional ports as
opposed to named ports.
Fourth: (Here comes the biggy!), I argue that declaring default wire and reg
types are not necessary. Assignments within procedural blocks are always to
reg types. Assignments outside of procedural blocks are always to wire types
(assign, instance and gate primitive outputs). Assignments to a variable
from both within and outside a procedural block is a syntax error ("Syntax
error: assignment to variable "foo" from both a procedural assignment (line
#x) and a non-procedural assignment (line #y) is illegal").
Optional wire and reg declarations would be permitted, and non-default
types, tri1, tri0, integer, etc. would still be required.
I always forget my output reg declarations and I frequently switch back and
forth between making an output assignment from within a procedural
assignment and with a continuous assignment without changing the type
declaration.
I believe this makes Verilog even easier to use and reduces redundant
typing. This would not break any existing models.
Regards - Cliff
<p>Subject: BTF - B09 - ANSI Declarations
Behavioral Task Force - Enhancement Request
Assigned Enhancement Request Number: B09
Enhancement Name (Description): ANSI Declarations
Date Submitted: 970319
Requestor: adamk@cyrix.com (Adam Krolnik)
Status: RO
Is enhancement intended to be synthesizable?: Yes
1. Verbosity of the module definition.
The requirement to name port signals twice and thrice to provide the
required attributes is extremely verbose. Rather than have three sections
to list these attributes, how about one. E.g.
module acontroller (req, ack, data, reset, clock, start, end, ad,
cbe, error, head, full, empty);
input req, reset, clock, start;
input [7:0] data;
output ack, end, full, empty, error;
reg ack, end, full, empty, start;
output [31:0] ad;
reg [31:0] ad;
output [3:0] cbe;
reg [3:0] cbe;
output [7:0] head;
reg [7:0] head;
<p>module acontroller
(
input req, reset, clock, start;
input[7:0] data;
reg output ack, end, full, empty;
output error;
reg output[31:0] ad;
reg output[7:0] head;
reg output[3:0] cbe;
);
From: mac@silicon-sorcery.com
Date: Wed, 19 Mar 97 14:22:50 PST
Let us label this proposal ANSI DECLARATIONS.
I would support this proposal.
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