From: Clifford E. Cummings (cliffc@europa.com)
Date: Fri May 02 1997 - 07:34:47 PDT
Subject: BTF - B08 - Comma separated sensitivity list (like VHDL)
Behavioral Task Force - Enhancement Request
Assigned Enhancement Request Number: B08
Enhancement Name (Description): Comma separated sensitivity list (like VHDL)
Date Submitted: 970218
Requestor: mac@silicon-sorcery.com (Mike McNamara)
Status: RO
Is enhancement intended to be synthesizable?: Yes
To simplify Verilog combinational modeling capability
Proposal: Add a @* combinational sensitivity list capability to Verilog
LRM wording: TBD
BNF addition: TBD
Abstract: Modeling combinational logic for synthesis requires that all
Left-Hand-Side (LHS) equation variables be listed in the sensitivity
list; otherwise, pre-synthesis Verilog simulations may not match post-
synthesis Verilog simulations. It is too easy to omit one or more inputs
from the sensitivity list, especially if there are many inputs in the
equations. Add a "@*" token to specify that all inputs should be
considered in the sensitivity list. Examples:
// Example #1
always @*
y = (a & b) | (c & d);
// Example #1 equivalent to
always @(a or b or c or d)
y = (a & b) | (c & d);
// Example #2
always @* begin
tmp1 = a & b;
tmp2 = c & d;
y = tmp1 | tmp2;
end
// Example #2 equivalent to
always @(a or b or c or d or e or tmp1 or tmp2) begin
tmp1 = a & b;
tmp2 = c & d;
y = tmp1 | tmp2;
end
// EDA vendor question: would the equivalent always block have to
// be equivalent to having tmp1 and tmp2 in the sensitivity list?
NOTE: Verilog users are excited about this proposed short-cut! This
enhancement request will not break any existing Verilog models.
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