From: Clifford E. Cummings (cliffc@europa.com)
Date: Fri May 02 1997 - 07:34:06 PDT
Subject: BTF - B07- Comma separated sensitivity list (like VHDL)
Behavioral Task Force - Enhancement Request
Assigned Enhancement Request Number: B07
Enhancement Name (Description): Comma separated sensitivity list (like VHDL)
Date Submitted: 970218
Requestor: cliffc@europa.com (Cliff Cummings)
Status: Passed (concept) BTF on 3/31/97
Is enhancement intended to be synthesizable?: Yes
To simplify Verilog modeling capability
Proposal: Add comma separated sensitivity lists to Verilog
LRM wording: TBD
BNF addition: TBD
Abstract: Standard Verilog sensitivity lists currently require "or"
separators which makes Verilog more verbose than VHDL. Example:
always @(a or b or c or d or e)
Permit comma-separated and "or"-separated sensitivity lists. Examples:
always @(a, b, c, d, e) // appropriate usage
always @(posedge clk, negedge rstn) // appropriate usage
always @(a or b, c, d or e) // clumsy, permitted but not encouraged?
Should the last example be permitted??
This enhancement request will not break any existing Verilog models.
===== Notes from BTF meeting held at IVC on 3/31/97=====
Comma-separated sensitivity lists shall be synonymous to or-separated
sensitivity lists.
Supported by the entire BTF
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