From: Clifford E. Cummings (cliffc@europa.com)
Date: Fri May 02 1997 - 07:33:34 PDT
Subject: BTF - B06 - Parameter passing by name (explicit & implicit)
Behavioral Task Force - Enhancement Request
Assigned Enhancement Request Number: B06
Enhancement Name (Description): Parameter passing by name (explicit & implicit)
Date Submitted: 970218
Requestor: kurt@wsfdb.com (Kurt Baty)
Status: Passed (concept) BTF on 3/31/97
Is enhancement intended to be synthesizable?: Yes
To improve Verilog modeling capability
Abstract: Verilog currently supports port connections by name or by
position. Verilog only permits module instance parameter passing by position
and to redefine the 3rd parameter in a module, the 1st and 2nd parameters
must also be passed, even if they do not change (a separate defparam
statement is also allowed).
LRM wording: TBD
BNF addition: Below is a possible proposal for changes/additions to the
BNF (BNF courtesy of Kurt Baty).
//-----------------------------------------------------------------
// Possible syntax changes to IEEE Standard 1364-1995 - pg. 137
// - adds ordered and named_parameter_assignments
//-----------------------------------------------------------------
parameter_value_assignment ::= # (list_of_parameter_assignments)
list_of_parameter_assignments ::=
ordered_parameter_assignment {, ordered_parameter_assignment} |
named_parameter_assignment {, named_parameter_assignment}
ordered_parameter_assignment ::= expression
named_parameter_assignment ::= . parameter_identifier ([expression])
===== Notes from BTF meeting held at IVC on 3/31/97=====
This capability shall only exist for parameters that you could otherwise
assign using #(param, param), à
6 - in favor
1 - Abstain - because the capability already exists
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