From: Vivek Sagdeo (vivek@professionals.com)
Date: Fri May 09 1997 - 10:34:29 PDT
The issues about signed arithmetic related to
sign extension while doing the signed arithmetic
must follow the rules of unsigned arithemtic (as
of current language definition). Even in unsigned arithemtic,
sign extension is done, and the same must hold true for the
signed arithemtic. I remember that in the original Verilog
definition, we we intended to extend the arithemtic to signed
arithmetic and knew that the unsigned operands are not adequate
to do all integer compuations. Even integer was taken to be
a 32 bit reg in the Verilog internals. Thus, the basic idea
of adding signed arithemtic is consistent with the language
design.
Thus, my signed arithemtic spec will read as the following 3 lines:
1. SIgned regs are declared using 'reg signed <size> <identifier>;'
syntax.
2. All signed quantities behave like integers and are extended
following the same rules of 1364.
3. All expressions containing signed and unsigned quantities are treated
as unsigned expressions. Even here, the sign extens
-- Vivek Sagdeo, PerformanCae cORP, Mountain View, CA 94041
www.veri-log.com, 1-888-VERILOG
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