From: vivek@veri-log.com
Date: Fri May 16 1997 - 10:55:14 PDT
At 05:04 PM 5/15/97 -0400, Mark Hummel wrote:
>.....
>>1. 'structure' declaration :
>> structure cpu_regs
>> reg [7:0] a;
>> reg [7:0] b;
>> reg [7:0] c;
>> endstructure
>>
>>The declarations inside can be any type of valid
>>Verilog declarations including vectors, memories (and multi-dimensional
>>arrays as in Verilog-97). However, while using these at ports in
>>module declarations or ports in module instances or
>>as parameters to tasks and functions, rules must be followed
>>of their use. These are explained in items 3 and 4 below.
>
>
>Will an array of structures be allowed?
>ex: structure cpu_regs regfiles[7:0];
> rega = regfiles[i].a;
>
>The combination of structures and arrays would be very useful for
>complex repetitive logic.
This is in addition to original spec. In general, Verilg only allows arrays of
nets and regs and 2-dimensional arrays of regs that are memories.
There is a BTF of adding multidimensional arrays.
I do not see any problems in adding arrays of structures as an additional
construct in the definition of structures as given in your example above.
>
>I would also assume that members of a structure can appear in a
>sensitivity list:
>ex: always @( regfiles[0].a ) ....
>
>This should only execute if the member 'a' changes. Note: 'a' could be another
>structure type.
Yes, this is a correct usage. Membersof structures can be used as event
sensitizers.
Again, interpretation of structures as concatenation of its elements is a valid
interpretation in this context as well.
-- Vivek
Vivek Sagdeo
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>
>
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