From: Mark Hummel (mdh@argo.net)
Date: Thu May 15 1997 - 14:04:06 PDT
.....
>1. 'structure' declaration :
> structure cpu_regs
> reg [7:0] a;
> reg [7:0] b;
> reg [7:0] c;
> endstructure
>
>The declarations inside can be any type of valid
>Verilog declarations including vectors, memories (and multi-dimensional
>arrays as in Verilog-97). However, while using these at ports in
>module declarations or ports in module instances or
>as parameters to tasks and functions, rules must be followed
>of their use. These are explained in items 3 and 4 below.
<p>Will an array of structures be allowed?
ex: structure cpu_regs regfiles[7:0];
rega = regfiles[i].a;
The combination of structures and arrays would be very useful for
complex repetitive logic.
I would also assume that members of a structure can appear in a
sensitivity list:
ex: always @( regfiles[0].a ) ....
This should only execute if the member 'a' changes. Note: 'a' could be another
structure type.
Mark
===============================================
Mark Hummel mdh@argo.net
Raquette Software (508)-541-1421
"Who is John Galt?" -- Ayn Rand
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