From: Vivek Sagdeo (vivek@professionals.com)
Date: Thu May 15 1997 - 08:35:48 PDT
All the points raised by Mike Mcnamara(mac@silicon-sorcery.com), Tan
(tan@silicon-sorcery.com) and Adam Kronolik (adamk@cyrix.com) relate to
the details of the proposed enhancement.
Here is a refined spec. that will address the 12 points in Mac and Tan's
messages and the issue of nesting and wire/reg from Adam.
1. 'structure' declaration :
structure cpu_regs
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
endstructure
The declarations inside can be any type of valid
Verilog declarations including vectors, memories (and multi-dimensional
arrays as in Verilog-97). However, while using these at ports in
module declarations or ports in module instances or
as parameters to tasks and functions, rules must be followed
of their use. These are explained in items 3 and 4 below.
2. Nesting of records:
Structures can include other structures within them just like
"C". The other structures must be declared separately.
3. Typedefs - This is a separate item and will be a new BTF item.
This is defined in the next mail message. As seen there, typedefs
are allowed on structures and other types. This allows one to
define names for types. However, structures define types without
typedefs in their own right. These can be reused using
'strucure sname s1, s2, s3;' like syntax just like in "C".
Thus, typedefs are really not required for the anticipated use
of structures but can add more readability ot Verilog code.
<p>4. Accessing capability within a structure using the '.'
s.a, s.b, s.c
This adds a scope and same symbol as scope is used here.
Using the same symbol as hierarchical references is consistent and
unambiguous.
5. Passing as parameter : Either the whole structure or parts can
be passed as a parameter to tasks and functions. Here, one
can look at the structure as a concatenation of the items
declared within the structure.
6. Using records on ports :
Structures can be used be used on ports. Again, their use can
be viewed as a concatenation of items declared within. Thus,
only structures whose equivalent valid concatenations are allowed
in Verilog HDL are usable on ports.
7. structures can be used on left or right side of assignments and their
use is equivalent to concatenation of its items.
8. Ramifications on implementation :
This BTF item and the next one on typedefs mainly affects the
compiler and not so much the simulator.
9. SYntax :
New Keywords : structure endstructure
From 1364 syntax, add module_structure_declaration to module_item_declaration
and also to block_structure_declaration to block_item_declaration.
module_structure_declaration ::= structure
module_item_declaration
{module_item__declaration}
endstructure
block_structure_declaration ::= structure
block_item_declaration
{block_item__declaration}
endstructure
In addition, all places where concatenations are used, add
strucure identifiers.
Add strucure item references to the hierarchical naming.
ANy other related changes while redefining complete bnf for 1364-97.
--- Vivek Sagdeo
PerformanCAE Corporation
http://www.veri-log.com
(888)-VERILOG
444 Castro St, Suite 408, Mountain View, CA 94041
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