From: Anders Nordstrom (andersn@bcarsb82)
Date: Mon Aug 11 1997 - 12:02:26 PDT
I would like to suggest that Verilog supports individual bit selects
in arrayed structures so that individual bits in an element can be
accessed as well as the entire element.
This would help in modeling and test bench writing. For example, in telecom
applications one often have to access individual bits in a vector stored in
a memory and use it for control.
Accessing individual bits should be allowed for the existing memory structures
in Verilog as well as for multi dimensional arrays as described in Enhancement
Request B02.
<p>With request B02 added, memories can be declared in two ways in Verilog:
reg [range1] memoryA [range2]; // range2 number of elements of size range1
reg memoryB [range1] [range2]; // range1 x range2 array of 1-bit values
examples:
reg [7:0] memoryA [63:0]; // 64 8-bit wide elements
reg [7:0] wordA;
reg bitA;
The following two assignment should be legal for memoryA:
initial begin
wordA <= memoryA[33]; //assign entire word to wordA
bitA <= memoryA[33][5]; //assig bit 5 of word 33 to bitA
end
reg memoryB [7:0] [63:0]; // 8 x 64 array of one bit values;
reg bitB;
Only the following assignment is legal for memoryB:
initial
bitB <= memoryB [33][5]; // the element is 1 bit wide
The same applies to multidimensional arrays.
reg [7:0] memoryC [799:0] [599:0]; // 800 x 600 array of 8 bit values
wire [7:0] wordC;
wire bitC;
The following two assignments should be legal:
assign wordC = memoryC [450][350]; // access entire element
assign bitC = memoryC [450][350][3] // bit 3 of the element
<p>+-----------------------------------------------------------------------+
| Anders Nordstrom |
| Northern Telecom Ltd. Email: andersn@nortel.ca |
| P.O. Box 3511 Station C Phone: 613-763-9186 |
| Ottawa, Ontario K1Y 4H7 Fax: 613-763-2626 |
+-----------------------------------------------------------------------+
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:54:41 PDT
and
sponsored by Boyd Technology, Inc.