From: Anders Nordstrom (andersn@bcarsb82)
Date: Tue Sep 02 1997 - 09:59:03 PDT
Behavioral Task Force - Errata Submission
Assigned Enhancement Request Number: BE44
Errata Name (Description): Empty Ports
Section: 12.1.2
Date Submitted: 970531
Requestor: Mitchell Perilstein
Status: Submitted (priority not yet assigned)
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
Section 12.1.2 says,
A connection can be a simple reference to a register or a net
identifier, an expression, or a blank. An expression can be used for
supplying a value to a module input port. A blank module connection
shall represent the situation where the port is not to be connected.
Judging by XL behavior, the following sentence should be added.
If all module connections are not connected, the commas are
optional. For example, the following are identical.
flop f1(,,,);
flop f1();
This sentence could also go near the other relevant paragraph:
The list of module connections shall be provided only for modules
defined with ports. The parentheses, however, are always
required. When a list of module connections is given, the first
element in the list shall connect to the first port, the second to
the second port, and so on. See section12.3 for a more detailed
discussion of ports and port connection rules.
--- Mitchell N. Perilstein [\] COMPASS Design Automation, Columbia MD USA mnp@compass-da.com Tel: 301-724-5938, Fax: 410-992-3536<p>+-----------------------------------------------------------------------+ | Anders Nordstrom | | Senior ASIC Designer | | | | Northern Telecom Ltd. Email: andersn@nortel.ca | | P.O. Box 3511 Station C Phone: 613-763-9186 | | Ottawa, Ontario K1Y 4H7 Fax: 613-763-2626 | +-----------------------------------------------------------------------+
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