From: Anders Nordstrom (andersn@bcarsb82)
Date: Fri Aug 22 1997 - 08:54:56 PDT
Subject: BTF - BE33 - Overly complex syntax for init_val
Behavioral Task Force - Errata Submission
Assigned Enhancement Request Number: BE33
Errata Name (Description): Overly complex syntax for init_val
Section: 8.1
Date Submitted: 970701
Requestor: Paul Graham
Status: Submitted (priority not yet assigned)
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
This is just a matter of taste, but why was it deemed necessary to
specify the syntax for init_val:
init_val ::= 1'b0 | 1'b1 | 1'bx | ... | 1 | 0
Since the output port must be a scalar, it follows that the initial value
must be a one-bit expression. Thus the syntax for init_val appears to be
redundant. The only new information it conveys is that the initial value
may not be 1'bz. But it also says that the initial value may not be 1'h1,
which is a perfectly reasonable 1-bit value. Why not just say that the
initial value may not be high impedance?
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| Senior ASIC Designer |
| Northern Telecom Ltd. Email: andersn@nortel.ca |
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