From: Anders Nordstrom (andersn@bcarsb82)
Date: Fri Aug 22 1997 - 08:54:54 PDT
Subject: BTF - BE21 - hierarchical instance names versus module names
Behavioral Task Force - Errata Submission
Assigned Enhancement Request Number: BE21
Errata Name (Description): hierarchical instance names versus
module names
Section: 12.4.1
Date Submitted: 961207
Requestor: Mitch Perilstein
Details:
The example in Verilog LRM Section 12.4.1 is not legal according to
the paragraph above it, because the expression "b.i = 1;" in module c refers
to a module name and not an instance name.
Experiments:
* XL accepts it.
* Veriwell and Viperfree do not accept it.
Regarding upwards name references, the XL manual says that module names are
to be used, not instance names. The LRM says instance names. Apparently,
both are used in practice (ie, XL). One question would be what is supposed
to happen if there is visible both a parent instance and a parent module
with the desired region name.
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| Anders Nordstrom |
| Senior ASIC Designer |
| Northern Telecom Ltd. Email: andersn@nortel.ca |
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