From: Eli Sternheim (eli@interhdl.com)
Date: Wed Aug 20 1997 - 18:01:02 PDT
...
The name of a module [or instance] is sufficient to identify the
module and its location in the hierarchy. A lower-level module can
reference items in a module above it in the hierarchy[. For variables
they can be referenced] if the name of the higher-level module [or
it's instance name] is known. [For tasks, functions and named blocks,
Verilog will look in the enclosing module for the name, until it is
found of the root of the hierarchy is reached. It will only search in
------^^<----------------- (should be "or until")
higher enclosing modules for the name, not instances. ] The syntax for
a[ hierarchical] reference is as follows:
...
Eli
Eli Sternheim interHDL, Inc.
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email: eli@interhdl.com
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