From: Anders Nordstrom (andersn@bcarsb82)
Date: Wed Aug 20 1997 - 07:26:50 PDT
Subject: BTF - BE18 - Hierarchical references
Behavioral Task Force - Errata Submission
Assigned Enhancement Request Number: BE18
Enhancement Name (Description): Hierarchical references
Date Submitted: 970630
Requestor: Adam Krolnik
Status: Submitted (priority not yet assigned)
Errors found in the Verilog LRM (IEEE 1364-1995).
The section numbers below are incorrect. They should be 12.4 for Hierarchical Names,
12.4.1 for Upwards Name Referencing and 12.5 for Scope Rules.
Regards
Anders
<p>Below is an editing of the existing text for sections 12.5, 12.5.1 and 12.6 that comprise the
definition of hierarchical references. The changes noted by [] define the current abilities of
Cadence Verilog XL wrt locating tasks, functions and named blocks without a hierarchical reference or with an instance name that are non-local to the current scope.
<p> Adam Krolnik
Verification Engineer
Cyrix, Corp.
Richardson TX. 75083
adamk@cyrix.com
---------------------------------------------------
12.5 Hierarchical Names.
Every identifier in a Verilog description has a unique hierarchical path name. The hierarchy of modules and the definition of items such as tasks and named blocks within the modules define these names. The hierarchy of names can be viewed as a tree structure, where each module instance, task, function or named begin - end or fork - join block defines a new hierarchical level, or scope, in a particular branch of the tree.
At the top of the name hierarchy are the names of modules of which no instances have been created. It is the root of the hierarchy. Inside any module, each module instance, task definition, function definition, and named begin-end or fork-join block defines a new branch of the hierarchy. Named blocks within named blocks and within tasks and functions also create new branches.
Each node in the hierarchical name tree is a separate scope with respect to identifiers. A particular identifier can be declared at most once in any scope. See section 12.6 for a discussion of scope rules.
Any named Verilog object can be referenced uniquely in its full form by concatenating the names of the modules[ or instance names,] tasks, functions, or blocks that contain it. Use the period character to separate each of the names in the hierarchy. The complete path name to any object starts at the top-level module. This path name can be used from any level in the description. The first node name in this path name can also be the top of a hierarchy that starts at the level where the path is being used. [This type of name allows downward referencing of items.]
12.5.1 Upwards Name referencing
The name of a module [or instance] is sufficient to identify the module and its location in the hierarchy. A lower-level module can reference items in a module above it in the hierarchy[. For variables they can be referenced] if the name of the higher-level module [or it's instance name] is known. [For tasks, functions and named blocks, Verilog will look in the enclosing module for the name, until it is found of the root of the hierarchy is reached. It will only search in higher enclosing modules for the name, not instances. ] The syntax for a[ hierarchical] reference is as follows:
<name_of_module[_or_instance]>.<name_of_item>
There can be no spaces within the reference. Example 12-11 demonstrates upward referencing. In this example, there are four modules, mod_a, mod_b, mod_c and mod_d. Each module contains an integer x. The highest level modules in this segment of a model hierarchy are mod_a and mod_d. There are two copies of module mod_b.x because both mod_a and mod_d both instantiate mod_b.X. There are four copies of mod_c.x because each of the two copies of mod_b.x instantiates mod_c.x twice.
12.6 Scope rules
The following four elements define a new scope in Verilog:
modules
tasks
function
named blocks
An identifier can be used to declare only one item within a scope. This rule means, for example, that it is illegal to declare two variables that have the same name, or to name a task the same as a variable within the same module, or to give a gate the same instance name as the name of the met connected to its output.
If an identifier is referenced directly (without a hierarchical path) within a task, function or named-block, it must be declared either locally within the task, function or named block, or within a module, task or named block that is higher in the same branch of the name tree that contains the task, function, or named block. If it is declared locally, then the local item is used; if not, the Verilog will search upward until if finds an item by that name[. If the item is a variable, it will stop at a module boundary; if the item is a task, function, or named block it continues to search higher-level modules until found.] Searching [for variables] crosses named block, task and function boundaries, not module boundaries. This fact means that tasks and functions can use and modify the variables within the containing module by name, without going through their ports.
[If an identifier is referenced with a hierarchical name, the
path can start with an instance name, module name, task, function, or named block. The names will be searched first at the current level, then in higher-level modules until found. Since both module names and instance names can be used, precedence is given to instance names if there is a module named the same as an instance name.]
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| Anders Nordstrom |
| Northern Telecom Ltd. Email: andersn@nortel.ca |
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