From: Daryl Stewart (Daryl.Stewart@cl.cam.ac.uk)
Date: Thu Sep 18 1997 - 04:19:34 PDT
andersn@nortel.ca said:
> 2). A right-hand side value change schedules a change to the left-hand
> side, then, before the first value has taken affect, another RHS
> change schedules a second change to the same value at a later time.
<p>I would like to point out that nowhere (that I've yet seen) in P1364 is the
following behaviour described. (Of course if it is, then I'm about to explain
the obvious ;)
Consider the code:
module inertia();
reg r1, r2;
wire #10 w;
assign #20 w = r1;
assign #30 w = r2;
initial begin $display("r1 r2 w");
$monitor("%b %b %b", r1, r2, w, $time);
r1 = 1;
r2 = 1;
#100 ; // Now w, r1 and r2 are 1'b1
r2 = 0;
#25 ;
r1 = 0;
end
endmodule
<p>The only explanation of inertial cancelling is given as: ``In situations where
the right hand side operand changes before a previous change has had time to
propagate to the left hand side, then the latest value change shall be the
only one to be applied'' (end of section 6.1.3).
Hence it might be expected that the assignment of 0 to r2 schedules a 1'bx for
(30+10) cycles after it occurs, and the assignment of 0 to r1 cancels this
since it occurs before the 1'bx is committed, leaving 1'b0 to be committed to
w at t=155.
This is not the case, and the 1'bx is in fact committed at t=140 anyway.
$verilog -q inertia.cv
r1 r2 w
1 1 x 0
1 1 1 40
1 0 1 100
0 0 1 125
0 0 x 140
0 0 0 155
I believe, this is due to Verilog-XL modelling the net-delay and driver delay
sections separately. In this example, the 1'b0 driven by r2 has completed #25
of the #30 delay in its driver delay section when r1 is assigned 0. It then
completes the remaining #5 and the #10 of the net delay before r1's 0 drive
completes its own #20 driver delay.
<p>A(n even) longer description of my observations is available at
http://www.cl.cam.ac.uk/users/djs1002/verilog.project/papers/combining_signals.
ps.gz
cheers
Daryl Stewart
RA to EPSRC Verilog Formal Equivalence Project
http://www.cl.cam.ac.uk/users/djs1002/verilog.project/
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