BTF - BE61 - Assignment to implicit and explicit nets

From: Anders Nordstrom (andersn@nortel.ca)
Date: Tue Sep 16 1997 - 11:34:34 PDT


Behavioral Task Force - Errata Submission

Assigned Enhancement Request Number: BE61
Errata Name (Description): Assignment to implicit/explicit nets
Section: 6.1.2, page 51
Date Submitted: 12/8/96
Requestor: Stu Sutherland

Status: Submitted (priority not yet assigned)

Errors found in the Verilog LRM (IEEE 1364-1995).

Details:
The first paragraph does not correctly define how existing
Verilog products handle implicit net declarations. Suggest the sentance be
modified to read: "The continuous assignment statement shall place a
continuous
assignment on a net data type. The net may be explicitly declared, or may
inherit an implicit declaration in accordance with the implicit declarations
rules defined in section 3.5."

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