From: Anders Nordstrom (andersn@nortel.ca)
Date: Tue Sep 16 1997 - 11:31:11 PDT
Behavioral Task Force - Errata Submission
Assigned Enhancement Request Number: BE55
Errata Name (Description): Implicit net type definition
Section: 3.5, page 16
Date Submitted: 12/8/96
Requestor: Stu Sutherland
Status: Submitted (priority not yet assigned)
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
The first paragraph states that only signals connected to a
primitive, UDP or module instance assume an implicit net declaration. The
third paragraph says the assumed data type is scalar. Verilog-XL and other
simulators also assume an implicit net data type for the left-hand side of
continuous assignments, and will assume a vector size if the net is connected
to a vectored port. The submitter believes there may be other circumstances
where an implicit vector net is assumed. The exact rules for assuming
implicit net types needs to be defined.
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| Anders Nordstrom |
| Senior ASIC Designer |
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| Northern Telecom Ltd. Email: andersn@nortel.ca |
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