Signed Verilog, and the BTF conference call

From: mac@silicon-sorcery.com
Date: Wed Sep 10 1997 - 12:15:21 PDT

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        I apologize to those not members of the BTF, but I am not
aware of an alias for just the BTF...

        We are discussing signed verilog, I'd like to ask that the
gentlemen from Cadence have a Verilog-XL simulator available during
the meeting, so we can propose tests (like J Bhasker's) to be run on
the fly to determine that we aren't legislating behaviour that makes
Verilog-XL's behaviour incorrect (unless that is our agreed to goal)

        I did the signed work at Chronologic, but that was 3-4 years
ago, and I am no longer with the company and all that; I think we'd
all be best served if there was a user and a verilog simulator
available during the conference call to run down tests.

        -mac

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