From: Ted Elkind (elkind@cadence.com)
Date: Wed Sep 10 1997 - 08:39:50 PDT
Hi Adam,
By controlling pulse limits, the delays in specify blocks can provide
transport delays, inertial delays, and anything in between (transport
and inertial delays are just opposite ends of a spectrum of
possibilities).
Providing this kind of capability in delays outside the specify block
is something I very much want to add. I've brought this up in our
sub-group discussions, but we haven't moved this to the front burner
as of yet. But if both sub-groups are interested in this feature then
maybe it makes sense to deal with it now.
Our vision of this feature includes the ability to specify and use
specparams outside the specify block, and the ability to annotate
specparams through the PLI (and thereby from SDF using the new LABELS
feature, where a LABEL matches with a GENERIC in VHDL and with a
specparam in Verilog).
I'd like to modify your proposal so that the "->" operator transforms
the delay into one that can take pulse limits. In this way
modification of the pulse limits can provide any timing behavior
desired, including normal pulse filtering and pulse filtering to the
error state.
An example:
Verilog description:
specparam dly = 100;
-> #dly event_a;
-> @(posedge clk) event_a;
-> repeat (2) @(posedge clk) event_a;
SDF description:
(CELL
(CELLTYPE "cache")
(INSTANCE test.top.asic2)
(LABEL
(ABSOLUTE
(dly 150)
)
)
)
This is the first time I've written something up on this proposal, and
feedback, comments and corrections are welcome.
Ted Elkind
Cadence Design Systems
(508) 262-6354
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