From: vsagdeo@veri-log.com
Date: Fri Sep 26 1997 - 10:01:36 PDT
At 04:21 PM 9/16/97 EDT, Anders Nordstrom wrote:
>Subject: BTF - BE54 - Unsigned registers
<p>BAD MSG:
>
Behavioral Task Force - Errata Submission
>
>Assigned Enhancement Request Number: BE54
>Errata Name (Description): Unsigned registers
>Section: 3.3.1, page 15
>Date Submitted: 12/8/96
>Requestor: Stu Sutherland
>
>Status: Submitted (priority not yet assigned)
>
>Errors found in the Verilog LRM (IEEE 1364-1995).
>
>Details:
>Third paragraph, last sentance states that registers shall be
>treated as unsigned. This contradicts section 4.1.6. Suggest the sentance be
>struck.
>
These are unsigned in the sense of not separating any bit as signed bit and
consistently preserving that.. The display of a register in binary will provide
'b1..... for a number with negative value assignment. regs are really bits and
whether a collection f bits is signed or unsigned is usually answered
as unsigned.....
Thus, explnantion should be added as to the meaning of 'unsigned'...
Vivek Sagdeo
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