Re: BTF - B19- Cadence signed arithmetic proposal

From: Thomas Fitzpatrick (tfitz@cadence.com)
Date: Thu Sep 25 1997 - 14:26:58 PDT

On Sep 25, 3:23pm, Adam Krolnik wrote:
> Subject: Re: BTF - B19- Cadence signed arithmetic proposal

<p>BAD MSG:
>
 A couple of questions regarding signed arithmetic.
>
> 1. What are the values of this register? 0 and 1, or 0 and -1?
>
> reg signed a;
>
> It says "signed" so shouldn't it be 0 and -1?
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        Yes, the two values are 0 and -1. Here's the example:

module onebit;
  reg signed a;
  initial begin
    a = 1'b0;
    $display("%d",a);
    a = 1'b1;
    $display("%d",a);
    end
endmodule

verilog -q onebit.v
0
-1

>
> 2. If I take a bit select, part select or concatenation, how can I
> make it signed? Is this what the $signed() operator is for?

        Yes. Bit select and part selects are unsigned, so use
     reg [3:0] r;
     reg signed [3:0] s;
     reg [7:0] a;

     initial begin
       r= a[3:0];
       s = $signed(r);
     end
>
> 3. How does one control sign extension? If I get it automatically, what can
> I do to not get sign extension.

        If any operand is unsigned, then all are coerced to be unsigned. To
prevent signed operands from being sign-extended, simply cast one of the
operands to $unsigned. If you want operands sign extended, then cast them all
to signed (if they're not already).
>
> 4. Arithmetic shift left seems redundant, what is the need?

        Yes, ASL is redundant, but it is included for completeness. 

-- 
---------------
Tom Fitzpatrick

Cadence Design Systems           Technical Marketing Manager
Product Engineering              Logic Design & Verification Business Unit
(508)446-6438                    x6438

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