From: Eli Sternheim (eli@interhdl.com)
Date: Wed Sep 24 1997 - 10:15:26 PDT
> From: "Thomas Fitzpatrick" <tfitz@cadence.com>
> Date: Tue, 23 Sep 1997 18:29:11 -0400
<p>BAD MSG:
>
Hi All,
>
> Well, now that the BTF has agreed on using signed operands to implement signed
> arithmetic instead of signed operators, there are only a couple of outstanding
> issues remaining with the B19 proposal. I'd like to address them here so that
> they can be discussed on Monday's conference call (even though I won't be able
> to attend). The two issues are:
...
Content-Length: 1084
X-Lines: 32
X-Status: $$$$
X-UID: 0000000227
Status: RO
It may be late in the game to come up with a new proposal, but I think
that this signed/unsigned is a mess. Yes, if you are a Verilog lawyer
you can find what the result should be but most of the users are not
(and should not be) lawyers. I have the following suggestion.
1. An expression can be composed of either bits/vectors or of
integers.
2. If you want to mix, you need to cast explicitly:
integer i, j;
reg [31:0] a, b;
...
a = vector(j) + b;
i = integer(a) + j;
3. Bitwise operations on integers are not permitted (including
shifts. If you want to shift an integer you either cast it or
divide/multiply by 2).
4. Widthed constants are vectors (even 13'd) and unwidthed constants
are integers. You can cast constants.
There. I already feel better for getting it of my chest.
Eli
Eli Sternheim interHDL, Inc.
4984 El Camino Real, Suite 210 Los Altos, CA. 94022-1433
phone: 415-428-4200 fax: 415-428-4201
email: eli@interhdl.com
web: http://www.interhdl.com ftp: ftp.interhdl.com
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:54:42 PDT
and
sponsored by Boyd Technology, Inc.