From: Anders Nordstrom (andersn@nortel.ca)
Date: Sat Oct 11 1997 - 16:03:51 PDT
Behavioral Task Force - Errata Submission
Assigned Errata Number: BE67
Errata Name (Description): The non-blocking assignment
Section: 9.2.2 page 100
Date Submitted: 970929
Requestor: Daryl Stewat
Status: Submitted (priority not yet assigned)
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
I can't find a report of this on the Errata list, but I'm not sure if it's
already been noted!
cheers
Daryl
<p>Section 9.2.2 "The non-blocking assignment" describes the behaviour of the
non-blocking assignments in "module evaluates2" in two steps, incorrectly:
+-----
| Step 1: The simulator evaluates the right hand sides of the non-blocking
| assignments and schedules the assignments of the new values at posedge c.
|
| Step 2: At posedge c, the simulator updates the left hand side of each
| non-blocking assignment statement.
+-----
| always @(posedge c) begin
| a <= b;
| b <= a;
| end
+-----
hould read:
+-----
| Step 1: at posedge c, the simulator evaluates the right hand sides of
| the non-blocking assignments and schedules the assignments of the new
| values at the end of the present simulation cycle.
|
| Step 2: At the end of the present simulation cycle, the simulator
| updates the left hand side of each non-blocking assignment statement.
+-----
+-----------------------------------------------------------------------+
| Anders Nordstrom |
| Senior ASIC Designer |
| |
| Northern Telecom Ltd. Email: andersn@nortel.ca |
| P.O. Box 3511 Station C Phone: 613-763-9186 |
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