From: Clifford E. Cummings (cliffc@europa.com)
Date: Fri May 02 1997 - 07:32:44 PDT
Subject: BTF - B04 - Re-entrant Tasks
Behavioral Task Force - Enhancement Request
Assigned Enhancement Request Number: B04
Enhancement Name (Description): Re-entrant Tasks
Date Submitted: 960227
Requestor: IVC96 (Cliff Cummings)
Status: RO
Is enhancement intended to be synthesizable?: No
To improve Verilog testing capability
Abstract: Verilog tasks currently are not re-entrant. Many engineers do
not even know the problem exists. Currently, each task call uses the
same registers used by previous calls to the same task, even if the task
was already invoked and is currently running; therefore, existing task
variables become overwritten.
Re-Entrant Task Problem Example:
Suppose a Communications Hub/Switch with 8 ports needs to be verified by
applying 17 different tests, including a null test (do nothing for x
amount of time), to the communications ports.
- Tests are to be applied randomly on each port.
- As a test finishes on a port, a new test is randomly selected and
applied.
One method would be to encapsulate each test as a separate task.
Initiating a task on one port while the same task is running on another
port would cause the initial task variables to be overwritten
A simulation could be half-way through test-task #7 on port 5, when
test-task #7 is initiated on port 3, causing the port-5 task values to
become corrupted.
Re-entrant tasks could solve this problem.
Re-Entrant Task possible proposal: Define a new Verilog key word: taskr?
Have task and taskr keywords, similar to case, casez, casex keywords.
Each time the taskr is called, a new copy of run-time variables is
created and maintained for each taskr invoked
VSG concerns: what does this do to simulator performance/acceleration?
Unknown
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