From: Clifford E. Cummings (cliffc@europa.com)
Date: Fri May 02 1997 - 07:32:40 PDT
Dear Behavioral Task Force:
Please print and bring a copy of these e-mails to Behavioral Task Force
meetings (I will not be printing extra copies).
This morning I will be sending out about 23 e-mails all starting with "BTF -
..." If you are not part of the Behavioral Task Force, please feel free to
delete the entire set of e-mails.
Below I have included a tab-separated list of enhancement requests that I
have compiled. If someone wants me to re-post the list with spaces instead
of tabs, let me know.
This list is my attempt to pull enhancement requests from e-mails that have
been exchanged over the past five months requesting numerous features. It
probably is not complete. There have been a couple of e-mails from Adam
Krolnik that have contained multiple enhancement requests and questions. I
have tried to extract the enhancement request to be tracked while ignoring
the questions. If there are missing enhancement requests, please resubmit them.
I would like to encourage anyone is making an enhancement request, or anyone
who is making a follow up to an enhancement request, to follow a few simple
guidelines that will make my life easier:
1. Please send only one enhancement request per e-mail (multiple e-mails
enhancement requests are fine)
2. Please place "BTF" in the subject header, followed by an abbreviated
enhancement description (use the current enhancement request number and
description to comment on previously entered enhancement requests.
I have tried to remove the Microsoft special characters from the Word files
but may have missed a few. Please let me know if you see any garbage
characters and I will correct them.
Thanks for your help and I look forward to meeting with many of you Monday
morning.
Regards - Cliff Cummings
<p>Enhan. Req. Enhancement Name (Description) Date Submitted Requestor Status
B1 Verilog Generate 960227 IVC96
B2 Multidimensional Arrays 960227 IVC96
B3 Enhance Verilog File I/O 960227 IVC96
B4 Re-entrant Tasks 960227 IVC96
B5 Verilog Configuration Capability 960227 IVC96
B6 Parameter passing by name (explicit & implicit) 970218 Kurt Baty
B7 Comma separated sensitivity list (like VHDL) 970218 Cliff Cummings
B8 Combinational sensitivity list @* 970218 Mike McNamara
B9 ANSI declarations 970319 Adam Krolnik
B10 Behavioral assignment to wire 970319 Adam Krolnik
B11 Automatic width extension beyond 32 bits 970319 Adam Krolnik
B12 Continuous assignment case expressions 970319 Adam Krolnik
B13 Mutable bit selects 970319 Adam Krolnik
B14 Initial assignments in register declarations 970319 Adam Krolnik
B15 Built-in sizeof(x) function 970319 Adam Krolnik
B16 Access to last specified bit 970319 Adam Krolnik
B17 Separate compilation capability - extern module 970320 Eli Sternheim
B18 Enumerated types 970320 Eli Sternheim
B19 Cadence signed arithmetic proposal 970409 Tom Fitzpatrick
B20 Pullup/pulldown optional X-drive time 970428 Austen Hypher
B21 Automatic initialization of integers to 0 970418 Adam Krolnik
B22 Define an algorithm for $random() 970418 Adam Krolnik
B23 Constant functions 970501 Kurt Baty
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// Cliff Cummings E-mail: cliffc@europa.com //
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