From: Clifford E. Cummings (cliffc@europa.com)
Date: Fri May 02 1997 - 07:32:39 PDT
Subject: BTF - B05 - Verilog Configuration Capability
Behavioral Task Force - Enhancement Request
Assigned Enhancement Request Number: B05
Enhancement Name (Description): Verilog Configuration Capability
Date Submitted: 960227
Requestor: IVC96 (Cliff Cummings)
Status: RO
Is enhancement intended to be synthesizable?: No
To improve Verilog testing capability
Abstract: What Are Configurations? A configuration file describes which
modules (source files) will be used during simulation.
Configurations can contain:
- all behavioral models
- all gate-level (structural) models
-a mix of behavioral and structural models
Different configuration files are used to increase testing productivity
by allowing slower gate-level models to be simulated with faster
behavioral models in a larger design; thereby improving simulation
efficiency.
One example of mixing gate and behavioral instances in the same design
is instantiating four identical adders into a model, 3 behavioral
adders, 1 gate-level adder.
The Cadence approach (not in the IEEE-1364 Standard)is the inclusion of
`uselib compiler directives in the source code, which requires multiple
source files for multiple configurations. I believe this is an
undesirable solution.
Possible proposals: The VSG may need to standardize some command
switches, including:
-f to call command files and source listing files
-y to specify library directories
+libext+.v to specify file extensions
-v to specify library files
Similarly, we may want to add command-line switches for configuration
purposes? These could be placed in a separate <configuration>.f file by
Verilog users?
+uselib+<source_directory_or_file>[+<optional_libext>]=<instance_name>[+
<instance_name>]*
+uselib+/proj/gates/adder.v=i2
+uselib+/proj/vlog+libext+.v+.p=i1+i3+i4
The above syntax still needs help! We should be seeking for a
simple/consistent syntax to address this issue. We should avoid a
complex VHDL-like solution to configurations.
I have had many Verilog students ask if environmental variables could be
used in .f files. I believe it is a good idea (except for PC-Verilog
compatibility?)
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