Re: How about only allowing stacked variables in functions

From: Mike McNamara (mac@surefirev.com)
Date: Mon Jan 05 1998 - 10:52:45 PST


Adam Krolnik writes:
>
>
> >I suggest only allowing rentrant functions but not reentrant tasks.
>
> It's funny, I was thinking of asking this question. Why should we
> only allow reentrant tasks? Why not reentrant functions and remove
> the restriction that reentrant functions consume no simulation
> time.
>
> >other scheduling features of tasks. I looked at adding this to Cver
>
> Steve, I've heard the name "Cver" but never knew what it was, could
> you enlighten me?
>
>
> >Adding rentrant (as an option?) variables to functions is easy and
> >does not cause scheduling problems because by definition functions
> >are executed instantaneously. Also it seems to me the various
> >needs for more programming langugage features can be solved by
> >writing reentrant functions.
>
> I disagree; the specific feature if allowing simulation time to
> pass while using the task multiple times is what is really wanted.
> When I think about reentrant, I am thinking multiple processes will
> call a task that consumes time to perform its operation.
>
> On the subject of allowing reentrant functions. I have heard that
> functions can consume no time because otherwise you would have race
> conditions. With the addition of reentrant functions, this concern
> seems to be solved. Are there other reasons for restricting
> functions from consuming time?

        The reason for the restriction that Verilog functions can
consume no time is so fuctions can be used anywhere a variable might
be used:

        assign a = b[f(c)];
        mod m1 (a,b,f(c));

        These constructs get real weird to think about if f(c)
contains #10.

        -mac



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