From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri Feb 20 1998 - 00:40:58 PST
BAD MSG:
Dear BTF -
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I have manually re-captured the BNF from the Verilog-1995 Standard. I did
this to help make modifications to the BNF electronically. In the process
of copying the BNF, I have discovered additional errata that I will discuss
with Anders.
I am sending out two e-mail messages. This e-mail has a text version of the
BNF. The second e-mail message will have an Office-97/Word-97 version of
the BNF, completed with different fonts and colored highlights to help spot
potential changes to the BNF. I am using te Word-97-colored version to help
me personally track potential BNF changes. I hope most of you will have
access to Word-97 as this version is much easier to follow.
The BNF is still not completed but I believe this is a good start.
I look forward to our conference call Friday morning.
Regards - Cliff Cummings
Key
Errata
Proposed enhancement
BNF prior to proposed enhancement
Work-in-progress?
Missing definition
Unreferenced definition
A.1 Source text
ource_text ::= { description }
description ::=
module_declaration
| udp_declaration
module_declaration ::=
module_keyword [ # list_of_private_parameters ] module_identifier [
list_of_ports ] ;
{ module_item } endmodule
module_keyword ::= module | macromodule
list_of_ports ::= ( port { , port } )
port ::=
[ port_expression ]
| . port_identifier ( [ port_expression ] )
port_expression ::=
port_reference
| { port_reference { , port_reference } }
port_reference ::=
port_identifier
| port_identifier [ constant_expression ]
| port_identifier [ msb_constant_expression : lsb_constant_expression ]
(Verilog 1995 begin)
module_item ::=
module_item_declaration
| parameter_override
| continuous_assign
| gate_instantiation
| udp_instantiation
| module_instantiation
| specify_block
| initial_construct
| always_construct
(Verilog 1995 end)
(Verilog 1998 - B01 begin)
module_item ::=
ungeneratable_module_item_declaration
| non_generated_module_item
| generated_instantiation
| specify_block
ungeneratable_module_item_declaration ::=
parameter_declaration
| input_declaration
| output_declaration
| inout_declaration
non_generated_module_item ::=
generatable_module_item_declaration
| parameter_override
| continuous_assign
| gate_instantiation
| udp_instantiation
| module_instantiation
| initial_construct
| always_construct
non_generated_module_item_or_null ::=
non_generated_module_item
| ;
generatable_module_item_declaration ::=
net_declaration
| reg_declaration
| integer_declaration
| real_declaration
| time_declaration
| realtime_declaration
| event_declaration
| task_declaration
| function_declaration
(Verilog 1998 - B01 end)
module_item_declaration ::=
parameter_declaration
| input_declaration
| output_declaration
| inout_declaration
| net_declaration
| reg_declaration
| integer_declaration
| real_declaration
| time_declaration
| realtime_declaration
| event_declaration
| task_declaration
| function_declaration
parameter_override ::= defparam list_of_param_assignments ;
A.2 Declarations
parameter_declaration ::= parameter list_of_param_assignments ;
list_of_param_assignments ::= param_assignment { , param_assignment }
param_assignment ::= parameter_identifier = constant_expression
input_declaration ::= input [ range ] list_of_port_identifiers ;
output_declaration ::= output [ range ] list_of_port_identifiers ;
inout_declaration ::= inout [ range ] list_of_port_identifiers ;
list_of_port_identifiers ::= port_identifier { , port_identifier }
(Verilog 1995 begin)
reg_declaration ::= reg [ range ] list_of_register_identifiers ;
event_declaration ::= event event_identifier { , event_identifier } ;
list_of_real_identifiers ::= real_identifier { , real_identifier }
list_of_register_identifiers ::= register_name { , register_name }
register_name ::=
register_identifier
| memory_identifier [ upper_limit_constant_expression :
lower_limit_constant_expression ]
range ::= [ msb_constant_expression : lsb_constant_expression ]
list_of_net_identifiers ::= net_identifier { , net_identifier }
(Verilog 1995 end)
(Verilog 1998 - B02 begin)
(Question - were multi-dimensional tasks and functions also going to be
permitted???)
(If this BNF is correct for multidimensional arrays, this will also be
added to automatic tasks, etc.)
reg_declaration ::= reg [ range ] list_of_regmem_identifiers ;
event_declaration ::= event list_of_event_identifiers ;
list_of_regmem_identifiers ::= register_name | memory_name { ,
register_name | memory_name }
memory_name ::= memory_identifier [ upper_limit_constant_expression :
lower_limit_constant_expression ]
list_of_register_identifiers ::= register_name { , register_name }
register_name ::= register_identifier [ dimension { , dimension }]
list_of_real_identifiers ::= real_identifier [ dimension { , dimension }]
{ , real_identifier [ dimension { , dimension }] }
list_of_event_identifiers ::= event_identifier [ dimension { , dimension }]
{ , event_identifier [ dimension { , dimension }] }
range ::= [ msb_constant_expression : lsb_constant_expression ]
dimension ::= [ dimension_constant_expression :
dimension_constant_expression ]
list_of_net_identifiers ::= net_identifier [ dimension { , dimension }] { ,
net_identifier [ dimension { , dimension }] }
(Verilog 1998 - B02 end)
time_declaration ::= time list_of_register_identifiers ;
integer_declaration ::= integer list_of_register_identifiers ;
real_declaration ::= real list_of_real_identifiers ;
realtime_declaration ::= realtime list_of_real_identifiers ;
net_declaration ::=
net_type [ vectored | scalared ] [ range ] [ delay3 ]
list_of_net_identifiers ;
| trireg [ vectored | scalared ] [ charge_strength ] [ range ] [ delay3 ]
list_of_net_identifiers ;
| net_type [ vectored | scalared ] [ drive_strength ] [ range ] [ delay3 ]
list_of_net_decl_assignments ;
net_type ::= wire | tri | tri1 | supply0 | wand | triand | tri0 | supply1 |
wor | trior
drive_strength ::=
( strength0 , strength1 )
| ( strength1 , strength0 )
| ( strength0 , highz1 )
| ( strength1 , highz0 )
| ( highz0 , strength1 )
| ( highz1, strength0 )
strength0 ::= supply0 | strong0 | pull0 | weak0
strength1 ::= supply1 | strong1 | pull1 | weak1
charge_strength ::= ( small ) | ( medium ) | ( large )
delay3 ::= # delay_value | # (delay_value [ , delay_value [ , delay_value ]
] )
delay2 ::= # delay_value | # (delay_value [ , delay_value ] )
delay_value ::= unsigned_number | parameter_identifier |
constant_mintypmax_expression
list_of_net_decl_assignments ::= net_decl_assignment { , net_decl_assignment }
net_decl_assignment ::= net_identifier = expression
(Verilog 1995 begin)
function_declaration ::=
function [ range_or_type ] function_identifier ;
function_item_declaration { function_item_declaration }
statement
endfunction
range_or_type ::= range | integer | real | realtime | time
function_item_declaration ::=
block_item_declaration
| input_declaration
(Verilog 1995 end)
(Verilog 1998 - B04 begin)
function_declaration ::=
function [ automatic ] [ range_or_type ] function_identifier ;
function_item_declaration { function_item_declaration }
statement
endfunction
range_or_type ::= range | integer | real | realtime | time
function_item_declaration ::=
automatic_block_item_declaration
| automatic_input_declaration
(Verilog 1998 - B04 end)
(Verilog 1995 begin)
task_declaration ::=
task task_identifier ;
{ task_item_declaration }
statement_or_null
endtask
task_item_declaration :: =
block_item_declaration
| input_declaration
| output_declaration
| inout_declaration
(Verilog 1995 end)
(Perhaps this block_item_declaration (no longer used in the task
definition) should be moved to the end of section A.6)
block_item_declaration ::=
parameter_declaration
| reg_declaration
| integer_declaration
| real_declaration
| time_declaration
| realtime_declaration
| event_declaration
(Verilog 1998 - B04 begin)
task_declaration ::=
task [ automatic ] task_identifier ;
{ task_item_declaration }
statement_or_null
endtask
task_item_declaration :: =
automatic_block_item_declaration
| automatic_input_declaration
| automatic_output_declaration
| automatic_inout_declaration
automatic_block_item_declaration ::=
parameter_declaration
| automatic_reg_declaration
| automatic_integer_declaration
| automatic_time_declaration
| automatic_real_declaration
| automatic_realtime_declaration
| automatic_event_declaration
automatic_input_declaration ::= input [ automatic ] list_of_port_identifiers ;
automatic_output_declaration ::= output [ automatic ]
list_of_port_identifiers ;
automatic_inout_declaration ::= inout [ automatic ] list_of_port_identifiers ;
automatic_reg_declaration ::= reg [ automatic ] [range]
list_of_regmem_identifiers ;
automatic_integer_declaration ::= integer [ automatic ]
list_of_register_identifiers ;
automatic_time_declaration ::= time [ automatic ]
list_of_register_identifiers ;
automatic_real_declaration ::= real [ automatic ] list_of_real_identifiers ;
automatic_realtime_declaration ::= realtime [ automatic ]
list_of_real_identifiers ;
automatic_event_declaration ::= event [ automatic ]
list_of_event_identifiers ;
(Verilog 1998 - B04 end)
A.3 Primitive instances
gate_instantiation ::=
n_input_gatetype [drive_strength] [delay2] n_input_gate_instance { ,
n_input_gate_instance } ;
| n_output_gatetype [drive_strength] [delay2] n_output_gate_instance { ,
n_output_gate_instance } ;
| enable_gatetype [drive_strength] [delay3] enable_gate_instance { ,
enable_gate_instance } ;
| mos_switchtype [delay3] mos_switch_instance { , mos_switch_instance } ;
| pass_switchtype pass_switch_instance { , pass_switch_instance } ;
| pass_en_switchtype [delay3] pass_en_switch_instance { ,
pass_en_switch_instance } ;
| cmos_switchtype [delay3] cmos_switch_instance { , cmos_switch_instance } ;
| pullup [pullup_strength] pull_gate_instance { , pull_gate_instance } ;
| pulldown [pulldown_strength] pull_gate_instance { , pull_gate_instance } ;
n_input_gate_instance ::= [name_of_gate_instance] ( output_terminal ,
input_terminal { , input_terminal } )
n_output_gate_instance ::= [name_of_gate_instance] ( output_terminal , {
output_terminal } , input_terminal )
enable_gate_instance ::= [name_of_gate_instance] ( output_terminal ,
input_terminal , enable_terminal )
mos_switch_instance ::= [name_of_gate_instance] ( output_terminal ,
input_terminal , enable_terminal )
pass_switch_instance ::= [name_of_gate_instance] ( inout_terminal ,
inout_terminal )
pass_en_switch_instance ::= [name_of_gate_instance] ( inout_terminal ,
inout_terminal , enable_terminal )
cmos_switch_instance ::= [name_of_gate_instance] ( output_terminal ,
input_terminal ,
ncontrol_terminal , pcontrol_terminal)
pull_gate_instance ::= [name_of_gate_instance] (output_terminal )
name_of_gate_instance ::= gate_instance_identifier [range]
pullup_strength ::=
( strength0 , strength1 )
| ( strength1 , strength0 )
| ( strength1 )
pulldown_strength ::=
( strength0 , strength1 )
| ( strength1 , strength0 )
| ( strength0 )
input_terminal ::= scalar_expression
enable_terminal ::= scalar_expression
ncontrol_terminal ::= scalar_expression
pcontrol_terminal ::= scalar_expression
output_terminal ::= terminal_identifier | terminal_identifier [
constant_expression ]
inout_terminal ::= terminal_identifier | terminal_identifier [
constant_expression ]
n_input_gatetype ::= and | nand | or | nor | xor | xnor
n_output_gatetype ::= buf | not
enable_gatetype ::= bufif0 | bufif1 | notif0 | notif1
mos_switchtype ::= nmos | pmos | rnmos | rpmos
pass_switchtype ::= tran | rtran
pass_en_switchtype ::= tranif0 | tranif1 | rtranif1 | rtranif0
cmos_switchtype ::= cmos | rcmos
<p>(Verilog 1995)
A.4 Module instantiation
(Verilog 1998)
A.4 Module and Generated instantiation
module_instantiation ::=
module_identifier [ parameter_value_assignment ] module_instance { ,
module_instance } ;
(Verilog 1995)
parameter_value_assignment ::= # ( expression { , expression } )
(Verilog 1998 - B06 begin)
parameter_value_assignment ::= # ( list_of_parameter_assignments )
list_of_parameter_assignments ::=
ordered_parameter_assignment { , ordered_parameter_assignment } |
named_parameter_assignment { , named_parameter_assignment }
ordered_parameter_assignment ::= expression
named_parameter_assignment ::= . parameter_identifier ( [expression] )
(Verilog 1998 end)
module_instance ::= name_of_instance ( [list_of_module_connections] )
name_of_instance ::= module_instance_identifier [ range ]
list_of_module_connections ::=
ordered_port_connection { , ordered_port_connection }
| named_port_connection { , named_port_connection }
ordered_port_connection ::= [ expression ]
named_port_connection ::= .port_identifier ( [ expression ] )
(Verilog 1998 - B01 begin)
genvar_declaration ::= genvar list_of_genvar_identifiers ;
list_of_genvar_identifiers ::=
genvar_identifier { , genvar_identifier }
generated_instantiation ::= generate { generate_item } endgenerate
generate_item_or_null ::= generate_item | ;
generate_item ::=
generate_conditional_statement
| generate_case_statement
| generate_loop_statement
| generate_block
| non_generated_module_item
generate_conditional_statement ::=
if ( genvar_expression ) generate_item_or_null [ else
generate_item_or_null ]
generate_case_statement ::= case ( genvar_expression )
genvar_case_item { genvar_case_item } endcase
genvar_case_item ::= genvar_expression { , genvar_expression } :
generate_item_or_null | default [ : ] generate_item_or_null
generate_loop_statement ::= for ( genvar_assignment ; genvar_expression ;
genvar_assignment ) generate_item
genvar_assignment ::= genvar_identifier = genvar_expression
generate_block ::= begin [ : generate_block_identifier ] { generate_item }
end
(Verilog 1998 - B01 end)
A.5 UDP declaration and instantiation
udp_declaration ::=
primitive udp_identifier ( udp_port_list ) ;
udp_port_declaration { udp_port_declaration }
udp_body
endprimitive
udp_port_list ::= output_port_identifier , input_port_identifier { ,
input_port_identifier }
udp_port_declaration ::=
output_declaration
| input_declaration
| reg_declaration
udp_body ::= combinational_body | sequential_body
combinational_body ::= table combinational_entry { combinational_entry }
endtable
combinational_entry ::= level_input_list : output_symbol ;
sequential_body ::= [ udp_initial statement ] table sequential_entry {
sequential_entry } endtable
udp_initial statement ::= initial udp_output_port_identifier = init_val ;
init_val ::= 1'b0 | 1'b1 | 1'bx | 1'bX | 1'B0 | 1'B1 | 1'Bx | 1'BX | 1 | 0
sequential_entry ::= seq_input_list : current_state : next state ;
seq_input_list ::= level_input_list | edge_input_list
level_input_list ::= level_symbol { level_symbol }
edge_input_list ::= { level_symbol } edge_indicator { level_symbol }
edge_indicator ::= ( level_symbol level_symbol ) | edge_symbol
current_state ::= level_symbol
next state ::= output_symbol | -
output_symbol ::= 0 | 1 | x | X
level_symbol ::= 0 | 1 | x | X | ? | b | B
edge_symbol ::= r | R | f | F | p | P | n | N | *
udp_instantiation ::= udp_identifier [ drive_strength ] [ delay2 ]
udp_instance { , udp_instance } ;
udp_instance ::= [ name_of_udp_instance ] ( output_port_connection ,
input_port_connection
{ , input_port_connection } )
name_of_udp_instance ::= udp_instance_identifier [ range ]
A.6 Behavioral statements
continuous_assign ::= assign [drive_strength] [delay3]
list_of_net_assignments ;
list_of_net_assignments ::= net_assignment { , net_assignment }
net_assignment ::= net_lvalue = expression
initial_construct ::= initial statement
(Verilog 1995)
always_construct ::= always statement
(Verilog 1998 - B08)
always_construct ::= always [ @* ] statement
tatement ::=
blocking_assignment ;
| non_blocking_assignment ;
| procedural_continuous_assignments ;
| procedural_timing_control_statement
| conditional_statement
| case_statement
| loop_statement
| wait_statement
| disable_statement
| event_trigger
| seq_block
| par_block
| task_enable
| system_task_enable
tatement_or_null ::= statement | ;
blocking_assignment ::= reg_lvalue = [ delay_or_event_control ] expression
non_blocking_assignment ::= reg_lvalue <= [ delay_or_event_control ]
expression
procedural_continuous_assignments ::=
| assign reg_assignment ;
| deassign reg_assignment ;
| force reg_assignment ;
| force net_assignment ;
| release reg_lvalue ;
| release net_lvalue ;
procedural_timing_control_statement ::=
delay_or_event_control statement_or_null
delay_or_event_control ::=
delay_control
| event_control
| repeat ( expression ) event_control
delay_control ::=
# delay_value
| # ( mintypmax_expression )
event_control ::=
@ event_identifier
| @ ( event_expression )
event_expression ::=
expression
| event_identifier
| posedge expression
| negedge expression
| event_expression or event_expression
| event_expression , event_expression (Verilog 1998 - B07)
conditional_statement ::=
| if ( expression ) statement_or_null [ else statement_or_null ]
case_statement ::=
| case ( expression ) case_item [ case_item ] endcase
| casez ( expression ) case_item [ case_item ] endcase
| casex ( expression ) case_item [ case_item ] endcase
case_item ::=
expression { , expression } : statement_or_null
| default [ : ] statement_or_null
loop_statement ::=
| forever statement (Verilog 1998 - BE10)
| repeat ( expression ) statement
| while ( expression ) statement
| for ( reg_assignment ; expression ; reg_assignment ) statement
reg_assignment ::= reg_lvalue = expression
wait_statement ::=
| wait ( expression ) statement_or_null
event_trigger ::=
| -> event_identifier ;
disable_statement
| disable task_identifier ;
| disable block_identifier ;
seq_block ::= begin [ : block_identifier { block_item_declaration } ] {
statement } end
par_block ::= fork [ : block_identifier { block_item_declaration } ] {
statement } join
task_enable ::= task_identifier [ ( expression { , expression } ) ] ;
system_task_enable ::= system_task_name [ ( expression { , expression } ) ] ;
system_task_name ::= $identifier Note: The $ may not be followed by a space.
A.7 Specify section
pecify_block ::= specify { specify_item } endspecify ;
specify_item ::=
specparam_declaration
| path_declaration
| system_timing_check
specparam_declaration ::= specparam list_of_specparam_assignments ;
list_of_specparam_assignments ::= specparam_assignment { ,
specparam_assignment }
specparam_assignment ::=
specparam_identifier = constant_expression
| pulse_control_specparam
pulse_control_specparam ::=
PATHPULSE$ = ( reject_limit_value [ , error_limit_value ] ) ;
|
PATHPULSE$specify_input_terminal_descriptor$specify_output_terminal_descriptor
= ( reject_limit_value [ , error_limit_value ] ) ;
limit_value ::= constant_mintypmax_expression
path_declaration ::=
simple_path_declaration ;
| edge_sensitive_path_declaration ;
| state_dependent_path_declaration ;
simple_path_declaration ::=
parallel_path_description = path_delay_value
| full_path_description = path_delay_value
parallel_path_description ::=
( specify_input_terminal_descriptor [ polarity_operator ] =>
specify_output_terminal_descriptor )
full_path_description
( list_of_path_inputs [ polarity_operator ] *> list_of_path_outputs )
list_of_path_inputs ::=
( specify_input_terminal_descriptor { , specify_input_terminal_descriptor }
list_of_path_outputs ::=
( specify_output_terminal_descriptor { , specify_output_terminal_descriptor }
specify_input_terminal_descriptor ::=
input_identifier
| input_identifier [ constant_expression ]
| input_identifier [ msb_constant_expression : lsb_constant_expression ]
specify_output_terminal_descriptor ::=
output_identifier
| output_identifier [ constant_expression ]
| output_identifier [ msb_constant_expression : lsb_constant_expression ]
input_identifier ::= input_port_identifier | inout_port_identifier
output_identifier ::= output_port_identifier | inout_port_identifier
polarity_operator ::= + | -
path_delay_value ::=
list_of_path_delay_expressions
| ( list_of_path_delay_expressions )
list_of_path_delay_expressions ::=
t_path_delay_expression
| trise_path_delay_expression , tfall_path_delay_expression
| trise_path_delay_expression , tfall_path_delay_expression ,
tz_path_delay_expression
| t01_path_delay_expression , t10_path_delay_expression ,
t0z_path_delay_expression ,
tz1_path_delay_expression , t1z_path_delay_expression ,
tz0_path_delay_expression
| t01_path_delay_expression , t10_path_delay_expression ,
t0z_path_delay_expression ,
tz1_path_delay_expression , t1z_path_delay_expression ,
tz0_path_delay_expression
t0x_path_delay_expression , tx1_path_delay_expression ,
t1x_path_delay_expression ,
tx0_path_delay_expression , txz_path_delay_expression ,
tzx_path_delay_expression
path_delay_expression ::= constant_mintypmax_expression
edge_sensitive_path_declaration ::=
parallel_edge_sensitive_path_description = path_delay_value
| full_edge_sensitive_path_description = path_delay_value
parallel_edge_sensitive_path_description ::=
( [ edge_identifier ] specify_input_terminal_descriptor =>
specify_output_terminal_descriptor [ polarity_operator ] :
data_source_expression ) )
full_edge_sensitive_path_description ::=
( [ edge_identifier ] list_of_path_inputs *>
list_of_path_inputs [ polarity_operator ] : data_source_expression ) )
data_source_expression ::= expression
edge_identifier ::= posedge | negedge
state_dependent_path_declaration ::=
if ( conditional_expression ) simple_path_declaration
| if ( conditional_expression ) edge_sensitive_path_declaration
| ifnone simple_path_declaration
ystem_timing_check ::=
$setup ( timing_check_event , timing_check_event , timing_check_limit [
, notify_register ] ) ;
| $hold ( timing_check_event , timing_check_event , timing_check_limit [ ,
notify_register ] ) ;
| $period ( controlled_timing_check_event , timing_check_limit [ ,
notify_register ] ) ;
| $width ( controlled_timing_check_event , timing_check_limit ,
constant_expression [ , notify_register ] ) ;
| $skew ( timing_check_event , timing_check_event , timing_check_limit [ ,
notify_register ] ) ;
| $recovery ( controlled_timing_check_event , timing_check_event ,
timing_check_limit [ , notify_register ] ) ;
| $setuphold ( timing_check_event , timing_check_event , timing_check_limit ,
timing_check_limit [ , notify_register ] ) ;
timing_check_event ::=
[timing_check_event_control] specify_terminal_descriptor [ &&&
timing_check_condition ]
specify_terminal_descriptor ::=
specify_input_terminal_descriptor
| specify_output_terminal_descriptor
controlled_timing_check_event ::=
timing_check_event_control specify_terminal_descriptor [ &&&
timing_check_condition ]
timing_check_event_control ::=
posedge
| negedge
| edge_control_specifier
edge_control_specifier ::= edge [ edge_descriptor [ , edge_descriptor ] ]
edge_descriptor ::=
01
| 10
| 0x
| x1
| 1x
| x0
timing_check_condition ::=
scalar_timing_check_condition
| ( scalar_timing_check_condition )
scalar_timing_check_condition ::=
expression
| ~ expression
| expression == scalar_constant
| expression === scalar_constant
| expression != scalar_constant
| expression !== scalar_constant
timing_check_limit ::= expression
scalar_constant ::=
1'b0 | 1'b1 | 1'B0 | 1'B1 | 'b0 | 'b1 | 'B0 | 'B1 | 1 | 0
notify_register ::= register_identifier
A.8 Expressions
(Verilog 1998 - B01 begin)
genvar_expression ::=
genvar_primary
| unary_operator genvar_primary
| genvar_expression binary_operator genvar_expression
| genvar_expression ? genvar_expression : genvar_expression
| string
genvar_primary ::=
constant_primary
| genvar_identifier
| genvar_identifier [ genvar_expression ]
| genvar_identifier [ msb_constant_expression : lsb_constant_expression ]
| genvar_concatenation | genvar_multiple_concatenation
| genvar_function_call
genvar_function_call ::= genvar_function_identifier ( genvar_expression { ,
genvar_expression } )
(Verilog 1998 - B01 end)
net_lvalue ::=
net_identifier
| net_identifier [ expression ]
| net_identifier [ msb_constant_expression : lsb_constant_expression ]
| net_concatenation
reg_lvalue ::=
reg_identifier
| reg_identifier [ expression ]
| reg_identifier [ msb_constant_expression : lsb_constant_expression ]
| reg_concatenation
constant_expression ::=
constant_primary
| unary_operator constant_primary
| constant_expression binary_operator constant_expression
| constant_expression ? constant_expression : constant_expression
| string
constant_primary ::=
number
| parameter_identifier
| constant_concatenation
| constant_multiple_concatenation
constant_mintypmax_expression ::=
constant_expression
| constant_expression : constant_expression : constant_expression
mintypmax_expression ::=
expression
| expression : expression : expression
expression ::=
primary
| unary_operator primary
| expression binary_operator expression
| expression ? expression : expression
| string
unary_operator ::=
+ | - | ! | ~ | & | ~& | | | ~| | ^ | ~^ | ^~
binary_operator ::=
+ | - | * | / | % | == | != | === | !== | && | ||
| < | <= | > | >= | & | | | ^ | ^~ | ~^ | >> | <<
(Verilog 1995 begin)
primary ::=
number
| identifier
| identifier [ expression ]
| identifier [ msb_constant_expression : lsb_constant_expression ]
| concatenation
| multiple_concatenation
| function_call
| ( mintypmax_expression )
(Verilog 1995 end)
(Verilog 1998 - B02 begin)
primary ::=
number
| identifier
| identifier [ expression ] { [ expression ] }
| identifier [ msb_constant_expression : lsb_constant_expression ]
| concatenation
| multiple_concatenation
| function_call
| ( mintypmax_expression )
(Verilog 1998 - B02 end)
number ::=
decimal_number
| octal_number
| binary_number
| hex_number
| real_number
real_number1 ::=
[ sign ] unsigned_number . unsigned_number
| [ sign ] unsigned_number [ . unsigned_number ] e [ sign ] unsigned_number
| [ sign ] unsigned_number [ . unsigned_number ] e [ sign ] unsigned_number
decimal_number1 ::=
[ sign ] unsigned_number
| [ size ] decimal_base unsigned_number
| [ size ] decimal_base x_z_digit { _ | x_z_digit } (Verilog 1998)
binary_number1 ::= [ size ] binary_base binary_digit { _ | binary_digit }
octal_number1 ::= [ size ] octal_base octal_digit { _ | octal_digit }
hex_number1 ::= [ size ] hex_base hex_digit { _ | hex_digit }
sign ::= + | -
size ::= unsigned_number
unsigned_number1 ::= decimal_digit { _ | decimal_digit }
decimal_base ::= 'd | 'D
binary_base ::= 'b | 'B
octal_base ::= 'o | 'O
hex_base ::= 'h | 'H
decimal_digit ::= 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 0
binary_digit ::= x | X | z | Z | 0 | 1
octal_digit ::= x | X | z | Z | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
hex_digit ::= x | X | z | Z | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | a | b
| c | d | e | f | A | B | C | D | E | F
(Verilog 1998)
x_z_digit ::= x | X | z | Z
concatenation ::= { expression { , expression } }
multiple_concatenation ::= { expression { , expression { , expression } } }
function_call ::=
function_identifier ( expression { , expression } )
| name_of_system_function [ ( expression { , expression } ) ]
name_of_system_function2 ::= $identifier
string ::= " { Any_ASCII_Characters_except_new_line } "
NOTES
1- Embedded spaces are illegal
2- The $ in name_of_system_function may not be followed by a space
A.9 General
comment ::=
short_comment
| long_comment
short_comment ::= // comment_text \n
long_comment ::= /* comment_text */
comment_text ::= { Any_ASCII_character }
identifier3 ::= IDENTIFIER [ { .IDENTIFIER } ]
IDENTIFIER ::=
simple_identifier
| escaped_identifier
simple_identifier ::= [a-zA-Z_] [ { [a-zA-Z0-9_$] } ] (Verilog 1998 - BE01)
escaped_identifier ::= \ {Any_ASCII_character_except_white_space} white_space
white_space ::= space | tab | newline
(Verilog 1995)
NOTE - The period in identifier may not be preceded or followed by a space
(Verilog 1998)
NOTE
3 - The period in identifier may not be preceded or followed by a space
<p>//********************************************************************//
// Cliff Cummings E-mail: cliffc@sunburst-design.com //
// Sunburst Design Phone: 503-579-6362 / FAX: 503-579-7631 //
// 15870 SW Breccia Dr., Beaverton, OR 97007 //
// //
// Verilog & Synthesis Training / On-Site Training //
// Verilog, VHDL, Synopsys, LMG, FPGA, Consulting and Contracting //
//********************************************************************//
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