From: Thomas Fitzpatrick (tfitz@cadence.com)
Date: Tue Feb 24 1998 - 10:49:31 PST
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Hi Adam,
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I've run this by one of our Verilog implementers here, and this is what
he thinks. Any other thoughts?
>
> I would rather build this stuff into the grammar than require
> additional downstream semantic checking. For example, there should be
> (I believe this was implied but not directly stated) semantic
> requirement that the part-select acutally has to look like
>
> expression : expression + constant_expression
> | expression + constant_expression : expression
>
> (permutations of + and -, commutative transformations etc., omitted)
>
> and that the "expression" in both the MSB and LSB portions have to be
> the same expression. His example fits this (spaces mine):
>
> qword_data[8*ith+7 : 8*ith]
>
> 8*ith is the expression, 7 is the constant_expression
>
> This semantic requirement ensures that the constant width requirement
> is met. This also requires the same piece of information to be
> represented twice, which leads to uneccessary duplication and also
> places the onus on the tools to ensure that the expressions are the
> same, thus it would have to allow:
>
> [8*ith+7 : ith*8]
> [3+7*foo:foo*7+8+3]
>
> etc., etc.
>
> Imagine the complexity of the checking for this. Therefore, I propose
> a syntax which only specifies the variable expression once, something
> like (I am very open to other suggestions):
>
> [8*ith +: 7] means [8*ith : 8*ith+7]
> or [8*ith -: 7] means [8*ith : 8*ith-7]
> [7 +: 8*ith] means [8*ith+7 : 8*ith]
> [7 -: 8*ith] means [8*ith-7 : 8*ith]
>
> It's pretty ugly, but this is only my quick and dirty idea, if someone
> can think of a better syntax I'm all for it, as long as it meets my
> desire for no semantic validation requirement.
>
<p>
-- --------------- Tom FitzpatrickCadence Design Systems Cobra Technical Marketing Manager Product Engineering Logic Design & Verification Business Unit (978)446-6438 x6438
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