From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Mon Mar 02 1998 - 00:49:01 PST
BTF Minutes - 03/02/98 - 9:00 AM-12:00 PM PST
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Status: RO
Attendees: Cliff Cummings, Anders Nordstrom, Tom Fitzpatrick, Karen Peiper,
Mike McNamara
Kurt Baty, Adam Krolnik,
B19 - Tom will review items listed in Stu Sutherland's e-mail. Tom will
check declaring signed on both ports and data-types. Tom to address ports
of different sizes to the busses being driven. Tom to check into VPI issues
related to the arithmetic proposal.
Cliff to contact Yatin: have Framemaker files sent to Kurt
Mike McNamara's File IO proposal looks good. Mike will put together a
proposal to be included in the Verilog spec. Mike will also look into an
fwrite binary mode enhancement.
Next BTF Meeting - Monday, 9:30AM start time at InterHDL
>We are located at 4984 El Camino Real. This is about half way between
>San Antonio and Rengstorff. We are just north of Carl's Junior
>restaurant, and accross the street from the "Off-Ramp" bike shop. From
>101 or Central Expwy take Rengstorff to El Camino, go right (North) on
>El Camino, past Carl's Junior on your left and when you see the
>Off-Ramp on your right, make a U turn and enter the parking lot.
>
>Eli
>
>--
>Eli Sternheim interHDL, Inc.
>4984 El Camino Real, Suite 210 Los Altos, CA. 94022-1433
>phone: 650-428-4200 fax: 650-428-4201
>email: eli@interhdl.com
>web: http://www.interhdl.com ftp: ftp.interhdl.com
Proposal made by the BTF: Outlaw nonblocking assignments within functions -
new enhancement (clarification).
Most Verilog simulators already treat nonblocking assignments as a syntax
error. Make this official.
B14 - integer a = 5; initial a = 7; - Verilog race condition -
"semantically equivalent to implementation as an initial block"
B15 - sizeof(a) function - mixed acceptance by the BTF - Adam to put
together a proposal to modify the 1364 standard.
B16 - Access to last specified bit - rejected in favor of a proposal for B15.
B17 - extern module proposal - no-one to champion this proposal at this
time - rejected - need more details from Eli. Verilog configuration
capability might add the desired functionality.
B18 - Enumerated types - mixed acceptance by the BTF - may require
attributes - need more details from Eli.
B20 - Pullup/pulldown optional X-drive time - mixed acceptance by the BTF
- Anders to put together a proposal to modify the 1364 standard.
B21 - Automatic init of integers to 0 - rejected in favor of B14
B22 - Define an algorithm for $random - Adam to put together a proposal to
modify the 1364 standard.
B23 - Constant functions - need a champion within a simulator vendor - we
will continue discussion of this proposal
B24 - `ifndef - already passed
B25 - Add struct / record data types - need a champion within a simulator
vendor - continue discussion
B26 - Part selects - ran out of time
Cliff to e-mail Eli to see if call-in capability will be available from
InterHDL
Old business - ran out of time
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