From: Adam Krolnik (adamk@cyrix.com)
Date: Tue Mar 03 1998 - 22:51:55 PST
Behavioral Task Force - Errata Submission
Assigned Enhancement Request Number: BE61
Errata Name (Description): Assignment to implicit/explicit nets
Section: 6.1.2, page 51
Date Submitted: 12/8/96
Requestor: Stu Sutherland
Status: Submitted (priority not yet assigned)
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
The first paragraph does not correctly define how existing
Verilog products handle implicit net declarations. Suggest the sentance(sic) be
modified to read:
"The continuous assignment statement shall place a continuous assignment
on a net data type. The net may be explicitly declared, or may inherit
an implicit declaration in accordance with the implicit declarations
rules defined in section 3.5."
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The current paragraph is as follows:
The continuous assignment statement shall place a continuous assignment on a
net that has been previously declared, either explicitly by declaration or
implicitly by using its name in the terminal list of a gate, user-defined
primitive, or module instance (see 3.5)
<p>While I don't see a difference in content between the two statements, I do
see Stu's suggestion to use the style of referring to other sections for
details rather than repeating them. Is there a specific detail in section 3.5
that I am overlooking?
<p>Recommendation:
Neutral acceptance of new wording.
<p> Adam Krolnik
Verification Engineer
Cyrix - NSM
Richardson TX. 75085
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