From: Stuart Sutherland (stuart@sutherland.com)
Date: Fri Mar 06 1998 - 20:49:12 PST
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Tom,
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Just a nit, but the following statement could be interpreted as conflicting
with the concept that the signed attribute can be declared at either the
port declaration or the net/register declaration.
>Page 15 (Section 3.3.1 Specifying vectors - 3rd Paragraph)
> Vector nets and registers shall obey laws of arithmetic modulo 2 to the
>power n(2^n), where n is the number of bits in the vector. Vector nets and
>registers shall be treated as unsigned quantities, unless the net or register
>is declared to be signed.
I think the wording proposed in section 12 about declaring the signed
attribute on either the port or the net/reg declaration is strong enough to
resolve any ambiguity. But, since the description about the signed
attribute on a port doesn't occur until much later (section 12), perhaps
more clear wording in this section might be to change the last sentence to:
Vector nets and registers shall be treated as unsigned quantities, unless
the net or register
is declared to be signed or is connected to a port that is declared to be
signed.
Stu
<p><p>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland.com
Specializing in Verilog HDL consulting and training. Publisher of the
popular Verilog HDL and Verilog PLI quick reference guides.
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