Re: BTF B19 - Signed Arithmetic Proposal (Updated)

From: Thomas Fitzpatrick (tfitz@cadence.com)
Date: Mon Mar 09 1998 - 06:02:27 PST

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Hi Shalom,
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Thanks for your input.

On Mar 8, 11:05am, Shalom Bresticker wrote:
> Subject: Re: BTF B19 - Signed Arithmetic Proposal (Updated)
> > From: "Thomas Fitzpatrick" <tfitz@cadence.com>
> > Date: Wed, 4 Mar 1998 10:44:10 -0500
> > Subject: BTF B19 - Signed Arithmetic Proposal (Updated)
> >
> > 6. Part-select results are unsigned, regardless of the operands.
>
> I have not followed the proposal very carefully,
> but I see a potential problem in this particular sentence.
>
> It is a common practice when using vectors to write it as a part-select of
> the entire vector, in order to emphasize the width of the vector. This
> reduces the likelihood of making a mistake.
>
> While doing so in some cases reduces simulator performance,
> it has never affected the functionality of the code, e.g.,
>
> wire [5:0] a,b,c ;
> a[5:0] = b[5:0] & c[5:0] ;
>
> and
>
> wire [5:0] a,b,c ;
> a = b & c ;
>
> were always the same.
>
> This sentence of the proposal would eliminate that possibilty for signed
operands.
>
> On the other hand, I agree that it is logical that part-selects should be
unsigned.
>
> I don't have a better idea, but maybe someone else does ?
>
> Sincerely,
> Shalom Bresticker
> ******************************************************************************
> Shalom Bresticker email: shalom@msil.sps.mot.com
> Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
> P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522444
> http://www.motorola-semi.co.il/
> ******************************************************************************
>-- End of excerpt from Shalom Bresticker

>From an implementation standpoint, we have tried very hard to minimize the
amount of checking that the parser has to do when it encounters an expression.
Having to check every part-select expression to see if it in fact covers the
entire vector would be unnecessary overhead which we would rather avoid.

Please note that adding the new functionality will not break any existing
designs, since you can currently only have things unsigned anyway. If you
insist on specifying part selects of full vectors, you could always use

 wire signed [5:0] a,b,c ;
 a[5:0] = $signed(b[5:0]) & $signed(c[5:0]) ;

Hope this helps,
-Tom 

-- 
---------------
Tom Fitzpatrick

Cadence Design Systems           Cobra Technical Marketing Manager
Product Engineering              Logic Design & Verification Business Unit
(978)446-6438                    x6438

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