From: Eli Sternheim (eli@interhdl.interhdl.com)
Date: Sun Apr 05 1998 - 16:06:34 PDT
It may be late but here is another request for Verilog extension. I
would like to add the directive `file. E.g.
`file myfile 156
This directive will typically be generated by a preprocessor and will
provide information to other tools downstream on where the code came
from. For example if the program vpp flattens `include files, and is
used to flatten the following:
file top.v
==========
module m;
`include "aa.inc"
endmodule
==========
file aa.inc
===========
reg r;
reg s;
==========
then the output from flattening would be:
==========
`file top.v 1
module m;
`file aa.inc 1
reg r;
reg s;
`file top.v 3
endmodule
==========
Eli
-- Eli Sternheim interHDL, Inc. 4984 El Camino Real, Suite 210 Los Altos, CA. 94022-1433 phone: 650-428-4200 fax: 650-428-4201 email: eli@interhdl.com web: http://www.interhdl.com ftp: ftp.interhdl.com
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