From: Adam Krolnik (adamk@cyrix.com)
Date: Mon Apr 06 1998 - 20:22:12 PDT
Behavioral Task Force - Errata Submission
Assigned Enhancement Request Number: BE39
Errata Name (Description): Task I/O Syntax
Section: 10.2.1
Date Submitted: 970103
Requestor: Mitchell Perilstein
Status: Submitted (priority not yet assigned)
Errors found in the Verilog LRM (IEEE 1364-1995).
Details:
Hi all,
LRM Sec 10.2.1 needs a little more detail regarding how a task
declaration's input/output declarations interact with its
block_item_declarations in the task scope.
In particular, Sec 10.2.1 says the i/o decls have the same syntax
as module decls in Sec 12; however, Sec 12 also specifies that if
there is an explict declaration of a port, it must match the i/o
decl. This would not appear to be so with tasks both in the LRM
and in the state of the art. (Maybe function declarations need
looking at, also?)
task Foo;
output [64:0] x;
reg [31:0] x;
//
// what is x?
//
endtask
XL accepts this sort of thing and I believe the model ends up
behaving as if it had a 32-bit output in this example.
--------------------------------------------------------------
Proposal:
In the last paragraph in section 10.2.1 "Defining a task", the first sentence
reads:
"These [task] declarations have the same syntax as the corresponding declarations in
in a module definition (see Section 12)."
Rather than refer to Section 12, I recommend:
'(see section 12.3.2 "Port Declarations" and section 3.2.2 "Registers")'
In section 12.3.2 is the sentence describing the behavior that Mitchell pointed
out.
[ I would also recommend this change to provide more consistency in the titles of
headings.
Propose an alternate title for sections 3.2.1 "Nets", 3.2.2 "Registers",
10.2.1 "Defining a task" and 10.3.1 "Defining a function".
New titles are:
"3.2.1 Net Declarations"
"3.2.2 Register Declarations"
"10.2.1 Task Declarations"
"10.3.1 Function Declarations"
These match section 12.3.2 "Port Declarations".
How would everyone feel if I asked for a larger "Contents" listing? One that included all
header sections?]
<p> Adam Krolnik
Verification Engineer
Cyrix - NSM.
Richardson TX. 75085
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