From: Adam Krolnik (adamk@cyrix.com)
Date: Tue Apr 14 1998 - 22:56:44 PDT
Eli wrote:
>A very good point. Another ugly feature of `timescale is that it can
>appear anywhere inside a module. I am not sure if it means that the
XL forbids the timescale directive inside a module, but VCS allows it. Maybe this
should be standardized also.
Adam
<p>timet.v
----------
`timescale 10ns / 1ns
module test;
`timescale 1ns / 1ns
initial begin
#20.4 $display("%m: time is %0t.", $realtime);
end
endmodule
--------------------
verilog -q timet.v
Error! Compiler directive not allowed inside a module [Verilog-CDNAM]
"timet.v", 6:
Error! syntax error [Verilog]
"timet.v", 6: `timescale 1<-
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