From: Shalom Bresticker (shalom@msil.sps.mot.com)
Date: Sun Apr 19 1998 - 00:26:06 PDT
BAD MSG:
I reported this to Cadence a year ago,
nd they confirmed it is a syntax error which the compiler should catch.
Content-Length: 1626
X-Lines: 63
X-Status: $$$$
X-UID: 0000000393
Status: RO
It was scheduled to be fixed in the next release of Verilog-XL,
which was 97B. I cannot confirm that, as I have only the 97A release.
Possibly VCS accepts it only to be compatible with Verilog-XL.
******************************************************************************
Shalom Bresticker email: shalom@msil.sps.mot.com
Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522444
http://www.motorola-semi.co.il/
******************************************************************************
<p>> From owner-btf@boyd.com Tue Apr 14 21:05:40 1998
> From: Adam Krolnik <adamk@cyrix.com>
> Date: Mon, 13 Apr 98 17:38:09 +0600
> To: btf@boyd.com
> Subject: Unspecified abilities on instantiation of modules.
>
>
> I don't see anywhere in the BNF how you can specify the drive strength for
> a plain module instantiation.
>
> Both XL and VCS accept this, yet it isn't documented anywhere.
>
> What should be done with this? Erratta?
>
> Adam Krolnik
> Verification Engineer
> Cyrix - NSM.
> Richardson TX. 75085
>
>
> --------------------------------------------------
> module top;
>
> wire y,a,b;
>
> // Hey, I get to specify strengths! Useless!!
> adam (weak0, strong1) #(5,5) n2(y,a,b);
>
> endmodule
>
>
> module adam( Y, A, B);
>
> parameter tr = 1;
> parameter tf = 1;
> parameter m = 1;
>
> input A, B;
> output Y;
>
>
> initial begin
> $display("The parameters are %0d %0d %0d.", tr,tf, m);
> end
>
> // Here are valid drive strength parameters!!
> nor (strong0, strong1) #( tr, tf) G1(Y, A, B);
>
> endmodule
>
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:52:48 PDT
and
sponsored by Boyd Technology, Inc.