From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Wed Apr 22 1998 - 11:06:17 PDT
X-Lines: 120
Content-Type: text/plain; charset="us-ascii"
Content-Length: 4509
X-Status: $$$$
X-UID: 0000000408
Status: RO
B02: Multi-Dimensional Arrays
The Behavioral Task Force believes that all issues related to this
enhancement request have been addressed - we only need to prepare the
formal proposal
Action Item - Anders to send Multi-dimensional array e-mail to Mac and Vivek
Action Item - Mike McNamera to do the BNF
Action Item - Vivek to provide proposal verbiage for multidimensional arrays
NOTE: During our last conference call, it was determined that accessing
individual bits of memory words and multi-dimensional elements would be
required for certain forms of generated instances. Included at the end of
this e-mail is a re-post o Ander's proposal to accomplish this (B26).
I don't know what this means to the PLI??
B02 Notes -
(Use-Model #1 - additional ranges after the variable name) -
reg [range1a] variable1 [index2a] [index3a],
variable1 [index2a] [index3a];
wire [range1b] variable3 [index2b] [index3b],
variable4 [index2c] [index3c];
// Normal Verilog memory declaration follows
reg [range1d] memory_name [memory_range]; //memory
<p>Proposal: Multi-dimensional array declarations shall consist of:
net & reg types [range] element [index1][index2]... ;
Proposed by Cliff Cummings - 2nd by Kurt Baty - pass 7-0-1
Proposal: A full index1,index2 of elements shall not be accessed in a
single reference. Proposed by Karen Pieper - 2nd Cliff Cummings- pass 7-0-1
Proposal: Referencing the elements of a multi-dimensional array is of the
form element[index1][index2]...; Proposal Kurt Baty - 2nd Tom Fitzpatrick -
pass 7-0-1
(in-work) Proposal: bit- or part-select indexing into a multi-dimensional
element - Anders
Note : Multi-dimentional reference as a port?
Note : Can only access elements - output ports
B26: Indexing memory elements
Kurt and Mac believe B01 implies the need for B26.
Action Item: Anders to re-send B26
Need to re-look at B02 to make sure that B26 covers bit-select and
part-select of multidimensional arrays.
We would like Karen's input on this subject before approval within the BTF
Subject: BTF - B26 - bit selects of elements in arrayed structures
Behavioral Task Force - Enhancement Request
Assigned Enhancement Request Number: B26
Enhancement Name (Description): bit selects of elements in arrayed
structures
Date Submitted: 970811
Requestor: Anders Nordstrom
Status: Submitted
Details:
I would like to suggest that Verilog supports individual bit selects
in arrayed structures so that individual bits in an element can be
accessed as well as the entire element.
This would help in modeling and test bench writing. For example, in telecom
applications one often have to access individual bits in a vector stored in
a memory and use it for control.
Accessing individual bits should be allowed for the existing memory structures
in Verilog as well as for multi dimensional arrays as described in Enhancement
Request B02.
With request B02 added, memories can be declared in two ways in Verilog:
reg [range1] memoryA [range2]; // range2 number of elements of size range1
reg memoryB [range1] [range2]; // range1 x range2 array of 1-bit values
examples:
reg [7:0] memoryA [63:0]; // 64 8-bit wide elements
reg [7:0] wordA;
reg bitA;
The following two assignment should be legal for memoryA:
initial begin
wordA <= memoryA[33]; //assign entire word to wordA
bitA <= memoryA[33][5]; //assig bit 5 of word 33 to bitA
end
reg memoryB [7:0] [63:0]; // 8 x 64 array of one bit values;
reg bitB;
Only the following assignment is legal for memoryB:
initial
bitB <= memoryB [33][5]; // the element is 1 bit wide
The same applies to multidimensional arrays.
reg [7:0] memoryC [799:0] [599:0]; // 800 x 600 array of 8 bit values
wire [7:0] wordC;
wire bitC;
The following two assignments should be legal:
assign wordC = memoryC [450][350]; // access entire element
assign bitC = memoryC [450][350][3] // bit 3 of the element
<p>//********************************************************************//
// Cliff Cummings E-mail: cliffc@sunburst-design.com //
// Sunburst Design Phone: 503-579-6362 / FAX: 503-579-7631 //
// 15870 SW Breccia Dr., Beaverton, OR 97007 //
// //
// Verilog & Synthesis Training / On-Site Training //
// Verilog, VHDL, Synopsys, LMG, FPGA, Consulting and Contracting //
//********************************************************************//
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:52:48 PDT
and
sponsored by Boyd Technology, Inc.