From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Wed Apr 22 1998 - 11:08:48 PDT
<IEEE 1364 Proposed Wording - Cliff Cummings>
Section 12.1.3 Generated instantiation
Generated instantiation allows one or more defined modules, user defined
primitives and/or Verilog gate primitives to be conditionally and/or
multiply instantiated into a design. Generated instances have unique
identifier names and may be referenced hierarchically as described in
section #.#.
All generate statements are coded within a module scope and require the
keywords generate-endgenerate.
Connections to generated module instances are handled the same way as they
are handled with normal module instances as described in section 12.1.2.
Generated instances are created using one of the following three methods:
generate-loop, generate-conditional or generate-case.
Section 12.1.3.1 Generate-loop
A generate-loop permits one or more defined modules, user defined
primitives and/or Verilog gate primitives to be instantiated multiple times
using an indexed for-loop. The index loop-variable used in a generate
for-loop shall be declared as a genvar and is referred to as a genvar in
the rest of this section.
A genvar is a positive integer that is local to and shall only be used
within a generate scope.
<p>A genvar shall be declared within the module where the genvar is used. A
genvar can be declared either inside or outside of the generate-loop.
<p>Section 12.1.3.2 Generate-conditional
A generate-conditional is an if-else-if generate construct that permits one
or more defined modules, user defined primitives and/or Verilog gate
primitives to be conditionally instantiated into another module based on an
expression that is deterministic at the time the design is compiled.
Section 12.1.3.3 Generate-case
A generate case construct permits one or more defined modules, user defined
primitives and/or Verilog gate primitives to be conditionally instantiated
into another module based on a select one-of-many case construct. The
selecting case expression must be a run-time constant.
Example:
generate
case (WIDTH)
1: adder_1bit (co, sum, a, b, ci); // 1-bit adder implementation
2: adder_2bit (co, sum, a, b, ci); // 2-bit adder implementation
default: adder_cla (co, sum, a, b, ci); // others - carry look-ahead adder
endcase
endgenerate
<p>B01 Notes:
nested "generate" for-loops
Proposal: generate - endgenerate can only exist at the module scope - pass
5-2-1 (opposing - no new keywords should be introduced)
Proposal: genvar - for the generate for-loop: a generate-loop index
variable should be declared - pass 6-0-2
Proposal: new keyword genvar required - pass 6-1-1 (opposing - no new
keywords should be introduced)
Proposal: genvar is local to (may only be used within) the generate-scope -
pass 7-0-0
Proposal: genvar shall be declared within the module, either inside or
outside of the generate-loop, and its scope is the scope of the module.
Proposed by Kurt Baty - 2nd by Mike McNamara - pass 7-0-0
Proposal: case may test against an expression made up of constants and/or
genvars - Proposed by Mike McNamara - 2nd Kurt Baty - pass 7-0-0
Proposal: if-then-else may test against an expression made up of constants
and/or genvars - Proposed by Mike McNamara - 2nd Kurt Baty - pass 7-0-0
Proposal: Multiple square brackets are allowed in the instance hierarchical
reference, the bracketed values are constant expressions and can optionally
be followed with a period and another hierarchical reference. Proposed by
Kurt Baty - 2nd by Anders Nordstrom - pass 7-0-0
<p>Note : must avoid name collision
Note : would require ACC routines (PLI)
Note : genvar index would be part of the instance reference
Note : will not use variables in the genvar
Note : PLI - would like to see more about parameter overiding in the
proposal - down-bound parameter
Note : Give full intent of the enhancement in the beginning (ie - include
intent to include constant_functions)
Note : Where are negative values allowed???
Note : module_item_declaration should not include I/O
Note : nested for-loops should not mess with each other's index variable
Note : genvars can only be tested in if's and case's when nested in the
for-loop
Note : reg (good), parameter (bad?)
//********************************************************************//
// Cliff Cummings E-mail: cliffc@sunburst-design.com //
// Sunburst Design Phone: 503-579-6362 / FAX: 503-579-7631 //
// 15870 SW Breccia Dr., Beaverton, OR 97007 //
// //
// Verilog & Synthesis Training / On-Site Training //
// Verilog, VHDL, Synopsys, LMG, FPGA, Consulting and Contracting //
//********************************************************************//
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:52:48 PDT
and
sponsored by Boyd Technology, Inc.